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The ever-growing popularity of large language models (LLMs) has resulted in their increasing adoption for hardware design and verification.
J. Cong et al. , “High-level synthesis for fpgas: From prototyping to deployment,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol. 30, no. 4, pp. 473–491, 2011
2011
Earlier work this paper cites.
H. Pearce, B. Tan, and R. Karri, “Dave: Deriving automatically verilog from english,” in Proceedings of the 2020 ACM/IEEE Workshop on Machine Learning for CAD , ser. MLCAD ’20. New York, NY, USA: Association for Computing Machinery, 2020, p. 27–32. [Online]. Available: https://doi.org/10.1145/3380446.3430634
2020
Earlier work this paper cites.
F. Ferrandi et al. , “Invited: Bambu: an open-source research framework for the high-level synthesis of complex applications,” in 58th ACM/IEEE Design Automation Conference (DAC) . IEEE, Dec 2021, pp. 1327–1330
2021
Earlier work this paper cites.
2021
Earlier work this paper cites.
J. Cong et al. , “Fpga hls today: Successes, challenges, and opportunities,” ACM Trans. Reconfigurable Technol. Syst. , vol. 15, no. 4, aug 2022. [Online]. Available: https://doi.org/10.1145/3530775
2022
Earlier work this paper cites.
M. Liu et al. , “VerilogEval: evaluating large language models for verilog code generation,” in 2023 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) , 2023
2023
Earlier work this paper cites.
2023
Earlier work this paper cites.
2023
Earlier work this paper cites.
E. Nijkamp et al. , “Codegen: An open large language model for code with multi-turn program synthesis,” ICLR , 2023
2023
Earlier work this paper cites.
2023
Earlier work this paper cites.
J. Blocklove et al. , “Chip-chat: Challenges and opportunities in conversational hardware design,” in 2023 ACM/IEEE 5th Workshop on Machine Learning for CAD (MLCAD) . IEEE, Sep. 2023. [Online]. Available: http://dx.doi.org/10.1109/MLCAD58807.2023.10299874
2023
Earlier work this paper cites.
2023
Earlier work this paper cites.
2023
Earlier work this paper cites.
2023
Cited alongside, same era.
Y. Fu et al. , “Gpt4aigchip: Towards next-generation ai accelerator design automation via large language models,” in IEEE/ACM International Conference on Computer Aided Design (ICCAD) , 2023, pp. 1–9
2023
Cited alongside, same era.
AMD, “Vitis HLS,” https://docs.amd.com/r/en-US/ug1399-vitis-hls
2024
Cited alongside, same era.
2024
Cited alongside, same era.
M. Liu et al. , “VerilogEval,” https://github.com/NVlabs/verilog-eval
2024
Cited alongside, same era.
2024
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2024
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2024
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2024
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Cited alongside, same era.
R. Mukherjee, “HLSEval,” https://github.com/rijoym/HLSEval
2024
Cited alongside, same era.
S. Thakur et al. , “Verigen: A large language model for verilog code generation,” ACM Trans. Des. Autom. Electron. Syst. , vol. 29, no. 3, apr 2024. [Online]. Available: https://doi.org/10.1145/3643681
2024
Cited alongside, same era.
H. Wong, “HDLBits,” https://hdlbits.01xz.net/wiki/Problem_sets
2024
Cited alongside, same era.
2024
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B. Ahmad et al. , “On hardware security bug code fixes by prompting large language models,” IEEE Transactions on Information Forensics and Security , vol. 19, pp. 4043–4057, 2024
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R. Kande et al. , “(security) assertions by large language models,” IEEE Transactions on Information Forensics and Security , vol. 19, pp. 4374–4389, 2024
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H. Wu et al. , “Chateda: A large language model powered autonomous agent for eda,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , pp. 1–1, 2024
2024
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S. Williams, “The ICARUS Verilog Compilation System,” https://github.com/steveicarus/iverilog
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