Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework

Understand

Recent advances in large language models have demonstrated their potential for automated generation of hardware description language (HDL) code from high-level prompts.

• Researchers have utilized fine-tuning to enhance the ability of these large language models (LLMs) in the field of Chip Design.
• However, the lack of Verilog data hinders further improvement in the quality of Verilog generation by LLMs.
• Additionally, the absence of a Verilog and Electronic Design Automation (EDA) script data augmentation framework significantly increases the time required to prepare the training dataset for LLM trainers.