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2023

Using LLMs to Facilitate Formal Verification of RTL

Orenes-Vera, Marcelo, Martonosi, Margaret, Wentzlaff, David

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Formal property verification (FPV) has existed for decades and has been shown to be effective at finding intricate RTL bugs.

However, formal properties, such as those written as SystemVerilog Assertions (SVA), are time-consuming and error-prone to write, even for experienced users.
Prior work has attempted to lighten this burden by raising the abstraction level so that SVA is generated from high-level specifications.
However, this does not eliminate the manual effort of reasoning and writing about the detailed hardware behavior.

Using LLMs to Facilitate Formal Verification of RTL · Around

Built on

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Y. A. Manerkar, D. Lustig, M. Martonosi, and M. Pellauer, “RTLCheck: Verifying the memory consistency of RTL designs,” in
2017
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B.-Y. Huang, H. Zhang, P. Subramanyan, Y. Vizel, A. Gupta, and S. Malik, “Instruction-level abstraction (ILA): A uniform specification for system-on-chip verification,”
2018
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