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High Level Synthesis (HLS) tools offer rapid hardware design from C code, but their compatibility is limited by code constructs.
R. Nane, V.-M. Sima, C. Pilato, J. Choi, B. Fort, A. Canis, Y. T. Chen, H. Hsiao, S. Brown, F. Ferrandi, J. Anderson, and K. Bertels, “A survey and evaluation of fpga high-level synthesis tools,” IEEE Transactions on CAD , vol. 35, no. 10, pp. 1591–1604, 2016
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D. Soni, M. Nabeel, K. Basu, and R. Karri, “Power, area, speed, and security (pass) trade-offs of nist pqc signature candidates using a c to asic design flow,” in IEEE International Conference on Computer Design , 2019, pp. 337–340
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J. Blocklove, S. Garg, R. Karri, and H. Pearce, “Chip-chat: Challenges and opportunities in conversational hardware design,” in 2023 ACM/IEEE 5th Workshop on Machine Learning for CAD (MLCAD) , 2023, pp. 1–6
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S. Thakur, B. Ahmad, H. Pearce, B. Tan, B. Dolan-Gavitt, R. Karri, and S. Garg, “Verigen: A large language model for verilog code generation,” ACM Trans. Des. Autom. Electron. Syst. , feb 2024, just Accepted. [Online]. Available: https://doi.org/10.1145/3643681
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GeeksforGeeks, “Quick sort in c,” https://www.geeksforgeeks.org/quick-sort-in-c/ , accessed on 2024-04-06
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HLSLibs, “Hlslibs - high-level synthesis libraries,” https://hlslibs.org/ , accessed on 2024-04-06
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