Are LLMs Any Good for High-Level Synthesis?

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Chip-chat: Challenges and opportunities in conversational hardware design. In

Jason Blocklove, Siddharth Garg, Ramesh Karri, and Hammond Pearce. 2023 · 2023

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ChipGPT: How far are we from natural language hardware design

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Kaiyan Chang, Ying Wang, Haimeng Ren, Mengdi Wang, Shengwen Liang, Yinhe Han, Huawei Li, and Xiaowei Li. 2023 · 2023

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Gpt4aigchip: Towards next-generation ai accelerator design automation via large language models. In

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Llm-assisted generation of hardware assertions

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Efficient system-level design space exploration for high-level synthesis using pareto-optimal subspace pruning. In

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Verilogeval: Evaluating large language models for verilog code generation. In

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Leveraging High-Level Synthesis and Large Language Models to Generate, Simulate, and Deploy a Uniform Random Number Generator Hardware Design

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James T Meech. 2023 · 2023

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Generating secure hardware using chatgpt resistant to cwes

Madhav Nair, Rajat Sadhukhan, and Debdeep Mukhopadhyay. 2023 · 2023

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Using LLMs to Facilitate Formal Verification of RTL

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Marcelo Orenes-Vera, Margaret Martonosi, and David Wentzlaff. 2023 · 2023

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Benchmarking large language models for automated verilog rtl code generation. In

Shailja Thakur, Baleegh Ahmad, Zhenxing Fan, Hammond Pearce, Benjamin Tan, Ramesh Karri, Brendan Dolan-Gavitt, and Siddharth Garg. 2023 · 2023

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A survey of large language models

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Wayne Xin Zhao, Kun Zhou, Junyi Li, Tianyi Tang, Xiaolei Wang, Yupeng Hou, Yingqian Min, Beichen Zhang, Junjie Zhang, Zican Dong, et al · 2023

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On hardware security bug code fixes by prompting large language models

Baleegh Ahmad, Shailja Thakur, Benjamin Tan, Ramesh Karri, and Hammond Pearce. 2024 · 2024

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RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects

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Rtllm: An open-source benchmark for design rtl generation with large language model. In

Yao Lu, Shang Liu, Qijun Zhang, and Zhiyao Xie. 2024 · 2024

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A Multi-Expert Large Language Model Architecture for Verilog Code Generation

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Bardia Nadimi and Hao Zheng. 2024 · 2024

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Polyhedral Benchmark suite

Louis-Noël Pouchet and Tomofumi Yuki. 2012 · 2024

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AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design

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Ruidi Qiu, Grace Li Zhang, Rolf Drechsler, Ulf Schlichtmann, and Bing Li. 2024 · 2024

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Evaluating Large Language Models for Automatic Register Transfer Logic Generation via High-Level Synthesis

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Sneha Swaroopa, Rijoy Mukherjee, Anushka Debnath, and Rajat Subhra Chakraborty. 2024 · 2024