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Natural language interfaces have exhibited considerable potential in the automation of Verilog generation derived from high-level specifications through the utilization of large language models, garnering significant attention.
Prompting is programming: A query language for large language models
Beurer-Kellner, L., Fischer, M., and Vechev, M · 1969
Earlier work this paper cites.
Notational programming for notebook environments: A case study with quantum circuits
Arawjo, I., DeArmas, A., Roberts, M., Basu, S., and Parikh, T · 2022
Earlier work this paper cites.
Fixing hardware security bugs with large language models
Ahmad, B., Thakur, S., Tan, B., Karri, R., and Pearce, H · 2023
Earlier work this paper cites.
Chip-chat: Challenges and opportunities in conversational hardware design
Blocklove, J., Garg, S., Karri, R., and Pearce, H · 2023
Earlier work this paper cites.
Chipgpt: How far are we from natural language hardware design
Chang, K., Wang, Y., Ren, H., Wang, M., Liang, S., Han, Y., Li, H., and Li, X · 2023
Earlier work this paper cites.
Gpt4aigchip: Towards next-generation ai accelerator design automation via large language models
Fu, Y., Zhang, Y., Yu, Z., Li, S., Ye, Z., Li, C., Wan, C., and Lin, Y · 2023
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Chateda: A large language model powered autonomous agent for eda
He, Z., Wu, H., Zhang, X., Yao, X., Zheng, S., Zheng, H., and Yu, B · 2023
Earlier work this paper cites.
Llm-assisted generation of hardware assertions
Kande, R., Pearce, H., Tan, B., Dolan-Gavitt, B., Thakur, S., Karri, R., and Rajendran, J · 2023
Cited alongside, same era.
Unleashing the potential of llms for quantum computing: A study in quantum architecture design
Liang, Z., Cheng, J., Yang, R., Ren, H., Song, Z., Wu, D., Qian, X., Li, T., and Shi, Y · 2023
Cited alongside, same era.
VerilogEval: evaluating large language models for verilog code generation
Liu, M., Pinckney, N., Khailany, B., and Ren, H · 2023
Cited alongside, same era.
Rtllm: An open-source benchmark for design rtl generation with large language model, 2023
Lu, Y., Liu, S., Zhang, Q., and Xie, Z · 2023
Cited alongside, same era.
Chipnemo: Domain-adapted llms for chip design
Mingjie Liu§, T. E · 2023
Verigen: A large language model for verilog code generation
Thakur, S., Ahmad, B., Pearce, H., Tan, B., Dolan-Gavitt, B., Karri, R., and Garg, S · 2023
Later among the works it cites.
Rtlfixer: Automatically fixing rtl syntax errors with large language models
Tsai, Y., Liu, M., and Ren, H · 2023
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On the viability of using llms for sw/hw co-design: An example in designing cim dnn accelerators
Yan, Z., Qin, Y., Hu, X. S., and Shi, Y · 2023
Later among the works it cites.
Data is all you need: Finetuning llms for chip design via an automated design-data augmentation framework
Chang, K., Wang, K., Yang, N., Wang, Y., Jin, D., Zhu, W., Chen, Z., Li, C., Yan, H., Zhou, Y., Zhao, Z., Cheng, Y., Pan, Y., Liu, Y., Wang, M., Liang, S., yinhe han, Li, H., and Li, X · 2024
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The dawn of ai-native eda: Promises and challenges of large circuit models
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Cited alongside, same era.
From rtl to sva: Llm-assisted generation of formal verification testbenches, 2023
Orenes-Vera, M., Martonosi, M., and Wentzlaff, D · 2023
Cited alongside, same era.
Benchmarking large language models for automated verilog rtl code generation
Thakur, S., Ahmad, B., Fan, Z., Pearce, H., Tan, B., Karri, R., Dolan-Gavitt, B., and Garg, S · 2023
Cited alongside, same era.
Chen, L., Chen, Y., Chu, Z., Fang, W., Ho, T.-Y., Huang, Y., Khan, S., Li, M., Li, X., Liang, Y., et al · 2024
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Fang, W., Li, M., Li, M., Yan, Z., Liu, S., Zhang, H., and Xie, Z · 2024
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Hdldebugger: Streamlining hdl debugging with large language models
Yao, X., Li, H., Chan, T. H., Xiao, W., Yuan, M., Huang, Y., Chen, L., and Yu, B · 2024
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