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Driven by Moore's Law, the complexity and scale of modern chip design are increasing rapidly.
Mixture of experts: a literature survey
Saeed Masoudnia and Reza Ebrahimpour · 2014
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Deep reinforcement learning from human preferences
Paul F Christiano, Jan Leike, Tom Brown, Miljan Martic, Shane Legg, and Dario Amodei · 2017
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Hybrid actor-critic reinforcement learning in parameterized action space
Zhou Fan, Rui Su, Weinan Zhang, and Yong Yu · 2019
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Dreamplace: Deep learning toolkit-enabled gpu acceleration for modern vlsi placement
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Language models are few-shot learners
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Drills: Deep reinforcement learning for logic synthesis
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Retrieval-augmented generation for knowledge-intensive nlp tasks
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Dave: Deriving automatically verilog from english
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Learning to summarize with human feedback
Nisan Stiennon, Long Ouyang, Jeffrey Wu, Daniel Ziegler, Ryan Lowe, Chelsea Voss, Alec Radford, Dario Amodei, and Paul F Christiano · 2020
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On joint learning for solving placement and routing in chip design
Ruoyu Cheng and Junchi Yan · 2021
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A clock tree prediction and optimization framework using generative adversarial learning
Yi-Chen Lu, Jeehyun Lee, Anthony Agnesina, Kambiz Samadi, and Sung Kyu Lim · 2021
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A graph placement methodology for fast chip design
Azalia Mirhoseini, Anna Goldie, Mustafa Yazgan, Joe Wenjie Jiang, Ebrahim Songhori, Shen Wang, Young-Joon Lee, Eric Johnson, Omkar Pathak, Azade Nazi, et al · 2021
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Autosva: Democratizing formal verification of rtl module interactions
Marcelo Orenes-Vera, Aninda Manocha, David Wentzlaff, and Margaret Martonosi · 2021
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Learning transferable visual models from natural language supervision
Alec Radford, Jong Wook Kim, Chris Hallacy, Aditya Ramesh, Gabriel Goh, Sandhini Agarwal, Girish Sastry, Amanda Askell, Pamela Mishkin, Jack Clark, et al · 2021
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Generalizable floorplanner through corner block list representation and hypergraph embedding
Mohammad Amini, Zhanguang Zhang, Surya Penmetsa, Yingxue Zhang, Jianye Hao, and Wulong Liu · 2022
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The policy-gradient placement and generative routing neural networks for chip design
Ruoyu Cheng, Xianglong Lyu, Yang Li, Junjie Ye, Jianye Hao, and Junchi Yan · 2022
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Boils: Bayesian optimisation for logic synthesis
Antoine Grosnit, Cedric Malherbe, Rasul Tutunov, Xingchen Wan, Jun Wang, and Haitham Bou Ammar · 2022
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A timing engine inspired graph neural network model for pre-routing slack prediction
Zizheng Guo, Mingjie Liu, Jiaqi Gu, Shuhan Zhang, David Z Pan, and Yibo Lin · 2022
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Maskplace: Fast chip placement via reinforced visual representation learning
Yao Lai, Yao Mu, and Ping Luo · 2022
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Training language models to follow instructions with human feedback
Long Ouyang, Jeffrey Wu, Xu Jiang, Diogo Almeida, Carroll Wainwright, Pamela Mishkin, Chong Zhang, Sandhini Agarwal, Katarina Slama, Alex Ray, John Schulman, Jacob Hilton, Fraser Kelton, Luke Miller, Maddie Simens, Amanda Askell, Peter Welinder, Paul F Christiano, Jan Leike, and Ryan Lowe · 2022
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Functionality matters in netlist representation learning
Ziyi Wang, Chen Bai, Zhuolun He, Guangliang Zhang, Qiang Xu, Tsung-Yi Ho, Bei Yu, and Yu Huang · 2022
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Versatile multi-stage graph neural network for circuit representation
Zhihao Yang, Dong Li, Yingxueff Zhang, Zhanguang Zhang, Guojie Song, Jianye Hao, et al · 2022
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Bufformer: A generative ml framework for scalable buffering
Rongjian Liang, Siddhartha Nath, Anand Rajaram, Jiang Hu, and Haoxing Ren · 2023
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Rtllm: An open-source benchmark for design rtl generation with large language model
Yao Lu, Shang Liu, Qijun Zhang, and Zhiyao Xie · 2023
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Unlocking hardware security assurance: The potential of llms
Xingyu Meng, Amisha Srivastava, Ayush Arunachalam, Avik Ray, Pedro Henrique Silva, Rafail Psiakis, Yiorgos Makris, and Kanad Basu · 2023
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Generating secure hardware using chatgpt resistant to cwes
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Fixing hardware security bugs with large language models
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Chip-chat: Challenges and opportunities in conversational hardware design
Jason Blocklove, Siddharth Garg, Ramesh Karri, and Hammond Pearce · 2023
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Circuitnet: An open-source dataset for machine learning in vlsi cad applications with improved domain-specific evaluation metric and learning strategies
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Chipgpt: How far are we from natural language hardware design
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A deep learning framework for verilog autocompletion towards design and verification automation
Enrique Dehaerne, Bappaditya Dey, Sandip Halder, and Stefan De Gendt · 2023
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Gpt4aigchip: Towards next-generation ai accelerator design automation via large language models
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Large graph models: A perspective
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Circuitnet 2.0: An advanced dataset for promoting machine learning innovations in realistic chip design environment
Anonymous · 2024
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Preroutgnn for timing prediction with order preserving partition: Global circuit pre-training, local delay learning and attentional cell modeling
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