AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs

Understand

Assertion-based verification (ABV) is a critical method for ensuring design circuits comply with their architectural specifications, which are typically described in natural language.

• This process often requires human interpretation by verification engineers to convert these specifications into functional verification assertions.
• Existing methods for generating assertions from natural language specifications are limited to sentences extracted by engineers, discouraging its practical application.
• In this work, we present AssertLLM, an automatic assertion generation framework that processes complete specification files.