VeriGen: A Large Language Model for Verilog Code Generation

Understand

In this study, we explore the capability of Large Language Models (LLMs) to automate hardware design by generating high-quality Verilog code, a common language for designing and modeling digital systems.

• We fine-tune pre-existing LLMs on Verilog datasets compiled from GitHub and Verilog textbooks.
• We evaluate the functional correctness of the generated Verilog code using a specially designed test suite, featuring a custom problem set and testing benches.
• Here, our fine-tuned open-source CodeGen-16B model outperforms the commercial state-of-the-art GPT-3.5-turbo model with a 1.1% overall increase.