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The development of architecture specifications is an initial and fundamental stage of the integrated circuit (IC) design process.
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Z. He, H. Wu, X. Zhang, X. Yao, S. Zheng, H. Zheng, and B. Yu, “Chateda: A large language model powered autonomous agent for eda,” in MLCAD Workshop , 2023
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RISC-V ISA Specifications Volume 1, Unprivileged Specification , "https://wiki.riscv.org/display/HOME/RISC-V+Technical+Specifications"
Cited in the paper.
RISC-V ISA Specifications Volume 2, Privileged Specification , "https://wiki.riscv.org/display/HOME/RISC-V+Technical+Specifications"
Cited in the paper.
ARMv8-M Architecture Reference Manual , "https://documentation-service.arm.com/static/5f8efe85f86e16515cdbe596?token="
Cited in the paper.
Intel 64 and IA-32 Architectures Software Developer’s Manua , "https://cdrdv2.intel.com/v1/dl/getContent/671200"
Cited in the paper.
OpenRISC 1000 Architecture Manua , "https://openrisc.io/or1k.html"
Cited in the paper.
The NEORV32 RISC-V Processor: Datasheet , "https://stnolting.github.io/neorv32/"
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2023
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