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The Internet of Things (IoT) is an ongoing technological revolution.
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“Public-key cryptography standards (PKCS)# 1: RSA cryptography specifications version 2.1”, 2003
Jakob Jonsson and Burt Kaliski · 2003
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“Electrically programmable fuse (efuse): From memory redundancy to autonomic chips”
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“OSLO: Improving the Security of Trusted Computing.”
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“The 128-bit blockcipher CLEFIA”
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“Hardware Enforcement of Application Security Policies Using Tagged Memory.”
Nickolai Zeldovich, Hari Kannan, Michael Dalton and Christos Kozyrakis · 2008
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“An Embedded RISC-V Core with Fast Modular Multiplication”
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“Fully homomorphic encryption using ideal lattices”
Craig Gentry · 2009
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“Control-flow integrity principles, implementations, and applications”
Mart\’n Abadi, Mihai Budiu, Ulfar Erlingsson and Jay Ligatti · 2009
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“Research on Diffie-Hellman key exchange protocol”
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“An attack surface metric”
Pratyusa Manadhata and Jeannette Wing · 2010
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“Design, implementation, and evaluation of a vehicular hardware security module”
Marko Wolf and Timo Gendrullis · 2011
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“Big data security”
Colin Tankard · 2012
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“SMART: Secure and Minimal Architecture for (Establishing Dynamic) Root of Trust.”
Karim Eldefrawy, Gene Tsudik, Aur\’elien Francillon and Daniele Perito · 2012
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“NIST Special Publication 800-90A Recommendation for Random Number Generation Using Deterministic Random Bit Generators”
Elaine Barker and John Kelsey · 2012
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“Hardware/software codesign: The past, the present, and predicting the future”
J\"urgen Teich · 2012
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“Phantom: Practical oblivious computation in a secure processor”
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“LEA: A 128-bit block cipher for fast encryption on common processors”
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“Instruction sets should be free: The case for risc-v”
Krste Asanovi\’c and David Patterson · 2014
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“Micro-policies: Formally verified, tag-based security monitors”
Arthur De et al · 2015
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“Introduction to hardware security”
Yier Jin · 2015
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“Towards general purpose tagged memory”
Wei Song, Alex Bradbury and Robert Mullins · 2015
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“ARM® Memory Protection Unit (MPU)”
Ying Bai · 2016
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“Intel sgx explained.”
Victor Costan and Srinivas Devadas · 2016
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“The rocket chip generator”
Krste Asanovic et al · 2016
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“Hardware trojans: Lessons learned after one decade of research”
Kan Xiao et al · 2016
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“The Rocket Chip Generator”, 2016
Krste Asanović et al · 2016
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“Novel FPGA-based low-cost hardware architecture for the PRESENT block cipher”
Carlos Lara-Nino, Miguel Morales-Sandoval and Arturo Diaz-Perez · 2016
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“Report on post-quantum cryptography”
Lily Chen et al · 2016
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“Static and dynamic frequency scaling on multicore CPUs”
Wenlei Bao et al · 2016
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“PULPino: A small single-core RISC-V SoC”
Andreas Traber et al · 2016
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“Shakti-T: A RISC-V processor with light weight security extensions”
Arjun Menon et al · 2017
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“HOP: Hardware makes Obfuscation Practical”
Kartik Nayak et al · 2017
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“Secure silicon: Towards virtual prototyping”
Laurent Sauvage, Sofiane Takarabt and Youssef Souissi · 2017
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“Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications”
Pasquale Schiavone et al · 2017
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“Study of secure boot with a FPGA-based IoT device”
Yuan Liu, Jed Briones, Ruolin Zhou and Neeraj Magotra · 2017
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“Investigation on the optimal pipeline organization in RISC-V multi-threaded soft processor cores”
Mauro Olivieri et al · 2017
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“BOOMv2: an open-source out-of-order RISC-V core”
Christopher Celio et al · 2017
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“Hardware trojan detection through chip-free electromagnetic side-channel statistical analysis”
Jiaji He, Yiqiang Zhao, Xiaolong Guo and Yier Jin · 2017
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“A survey of timing channels and countermeasures”
Arnab Biswas, Dipak Ghosal and Shishir Nagaraja · 2017
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“Probing attacks on integrated circuits: Challenges and research opportunities”
Huanyu Wang, Domenic Forte, Mark Tehranipoor and Qihang Shi · 2017
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“Efficient tagged memory”
Alexandre Joannou et al · 2017
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“ { \{ CLKSCREW } \} : exposing the perils of security-oblivious energy management”
Adrian Tang, Simha Sethumadhavan and Salvatore Stolfo · 2017
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“Impact of big data on security”
Ramgopal Kashyap and Albert Piersson · 2018
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Moritz Lipp et al · 2018
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“Design and implementation of a dynamic information flow tracking architecture to secure a RISC-V core for IoT applications”
Christian Palmiero, Giuseppe Di, Luciano Lavagno and Luca Carloni · 2018
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“SiFive’s Trusted Execution Reference Platform”, 2018
Nate Graff Dabbelt · 2018
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“An energy-efficient reconfigurable DTLS cryptographic engine for End-to-End security in iot applications”
Utsav Banerjee, Chiraag Juvekar, Andrew Wright and Anantha Chandrakasan · 2018
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“Tmdfi: Tagged memory assisted for fine-grained data-flow integrity towards embedded systems against software exploitation”
Tong Liu et al · 2018
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“Design Exploration of SHA-3 ASIP for IoT on a 32-bit RISC-V Processor”
Jinli Rao et al · 2018
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“Binary Edwards Curves for Intrinsically Secure ECC Implementations for the IoT.”
Antoine Loiseau and Jacques Fournier · 2018
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“Evaluation of timing side-channel leakage on a multiple-target dynamic binary translator”
Otávio Napoli, Vanderson do Rosario, Diego de Freitas and Edson Borin · 2018
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“Blacklist core: machine-learning based dynamic operating-performance-point blacklisting for mitigating power-management security attacks”
Sheng Zhang et al · 2018
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“GAP-8: A RISC-V SoC for AI at the Edge of the IoT”
Eric Flamand et al · 2018
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“Secure boot and remote attestation in the sanctum processor”
Ilia Lebedev, Kyle Hogan and Srinivas Devadas · 2018
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“SWAN: Mitigating hardware trojans with design ambiguity”
Timothy Linscott, Pete Ehrett, Valeria Bertacco and Todd Austin · 2018
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“Hardware trojan attacks in embedded memory”
Tamzidul Hoque et al · 2018
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“K-Miner: Uncovering Memory Corruption in Linux.”
David Gens, Simon Schmitt, Lucas Davi and Ahmad-Reza Sadeghi · 2018
Cited alongside, same era.
“Secure VANETs: trusted communication scheme between vehicles and infrastructure based on fog computing”
Muhammad Arif, Guojun Wang and Valentina Balas · 2018
Cited alongside, same era.
“SecSVA: secure storage, verification, and auditing of big data in the cloud environment”
Gagangeet Aujla et al · 2018
Cited alongside, same era.
“FPGA-based remote power side-channel attacks”
Mark Zhao and G Suh · 2018
Cited alongside, same era.
“Translation leak-aside buffer: Defeating cache side-channel protections with { \{ TLB } \} attacks”
Ben Gras, Kaveh Razavi, Herbert Bos and Cristiano Giuffrida · 2018
Cited alongside, same era.
“ISA Semantics for ARMv8-a, RISC-v, and CHERI-MIPS”
Alasdair Armstrong et al · 2019
“The ai-based cyber threat landscape: A survey”
Nektaria Kaloudi and Jingyue Li · 2020
Later among the works it cites.
“Egalito: Layout-Agnostic Binary Recompilation”
David Williams-King et al · 2020
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“AI Acceleration with RISC-V for Edge Computing”
Chia-Hsiang Yang · 2020
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“Offline model guard: Secure and private ML on mobile devices”
Sebastian Bayerl et al · 2020
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Dominik Sisejkovic et al · 2020
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“RISC-V FPGA Platform Toward ROS-Based Robotics Application”
Jaewon Lee, Hanning Chen, Jeffrey Young and Hyesoon Kim · 2020
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Cited alongside, same era.
“IoT Signals report: IoT’s promise will be unlocked by addressing skills shortage, complexity and security” Accessed: 2020-01-15, https://blogs.microsoft.com/blog/2019/07/30
2019
Cited alongside, same era.
“Big data security challenges and strategies”
Sitalakshmi Venkatraman and Ramanathan Venkatraman · 2019
Cited alongside, same era.
“A very deep dive into iOS Exploit chains found in the wild ” Online; accessed 16 December 2020, https://googleprojectzero.blogspot.com/2019/08/a-very-deep-dive-into-ios-exploit.html
Ian Beer · 2019
Cited alongside, same era.
“33 Alarming Cybercrime Statistics You Should Know in 2019” Online; accessed 9 December 2020, https://securityboulevard.com/2019/11/33-alarming-cybercrime-statistics-you-should-know-in-2019
Casey Cane · 2019
Cited alongside, same era.
“Spectre attacks: Exploiting speculative execution”
Paul Kocher et al · 2019
Cited alongside, same era.
“PULP-NN: A Computing Library for Quantized Neural Network inference at the edge on RISC-V Based Parallel Ultra Low Power Clusters”
Angelo Garofalo et al · 2019
Cited alongside, same era.
Later among the works it cites.
“A prototype implementation and evaluation of the malware detection mechanism for IoT devices using the processor information”
Hayate Takase, Ryotaro Kobayashi, Masahiko Kato and Ren Ohmura · 2020
Later among the works it cites.
“An Energy-Efficient RISC-V RV32IMAC Microcontroller for Periodical-Driven Sensing Applications”
Ckristian Duran et al · 2020
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“Post-quantum secure boot”
Vinay Kumar et al · 2020
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“SaeCAS: Secure Authenticated Execution Using CAM-Based Vector Storage”
O. Arias, D. Sullivan, H. Shan and Y. Jin · 2020
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“Analyzing and enhancing embedded software technologies on RISC-V64 using the Ghidra framework”, 2020
Joris Both, Patrick Spaans, Alexandru Geana and Cees de Laat · 2020
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“Keystone: An open framework for architecting trusted execution environments”
Dayeol Lee et al · 2020
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“HECTOR-V: A Heterogeneous CPU Architecture for a Secure RISC-V Execution Environment”
Pascal Nasahl, Robert Schilling, Mario Werner and Stefan Mangard · 2020
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“Donky: Domain Keys–Efficient In-Process Isolation for RISC-V and x86”
David Schrammel et al · 2020
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“CURE: A Security Architecture with CUstomizable and Resilient Enclaves”
Raad Bahmani et al · 2020
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“Building Open Trusted Execution Environments”
David Kohlbrenner et al · 2020
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“PIE: A Dynamic TCB for Remote Systems with a Platform Isolation Environment”
Moritz Schneider et al · 2020
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“SoK: Understanding the prevailing security vulnerabilities in TrustZone-assisted TEE systems”
David Cerdeira, Nuno Santos, Pedro Fonseca and Sandro Pinto · 2020
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“RIMI: Instruction-level Memory Isolation for Embedded Systems on RISC-V”
H. Kim et al · 2020
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“Creating Foundations for Secure Microarchitectures With Data-Oblivious ISA Extensions.”
Jiyong Yu, Lucas Hsiung, Mohamad El and Christopher Fletcher · 2020
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“Hardware Assisted Buffer Protection Mechanisms for Embedded RISC-V”
Asmit De, Aditya Basu, Swaroop Ghosh and Trent Jaeger · 2020
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“Prevention of Microarchitectural Covert Channels on an Open-Source 64-bit RISC-V Core”
Nils Wistoff et al · 2020
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“Towards Provable Timing-Channel Prevention”
Gernot Heiser, Toby Murray and Gerwin Klein · 2020
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“Confidaent: Control FLow protection with Instruction and Data Authenticated Encryption”
Olivier Savry, Mustapha El-Majihi and Thomas Hiscock · 2020
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“Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process”
Kyndylan Nienhuis et al · 2020
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“SIMF: Single-Instruction Multiple-Flush Mechanism for Processor Temporal Isolation”
Tuo Li, Bradley Hopkins and Sri Parameswaran · 2020
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“Recommendations for a radically secure ISA”
Mathieu Escouteloup, Jacques Fournier, Jean-Louis Lanet and Ronan Lashermes · 2020
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“Capability hardware enhanced risc instructions: Cheri instruction-set architecture (version 8)”, 2020
Robert Watson et al · 2020
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“RISC-V Extension for Lightweight Cryptography”
E. Tehrani, T. Graba, A.. Merabet and J.. Danger · 2020
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“ISA Extensions for Finite Field Arithmetic”
Erdem Alkim et al · 2020
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“The design of scalar AES Instruction Set Extensions for RISC-V”, 2020
Ben Marshall et al · 2020
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“Virtual Secure Platform: A Five-Stage Pipeline Processor over TFHE”
Kotaro Matsuoka et al · 2020
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“Building a Modern TRNG: An Entropy Source Interface for RISC-V”
Markku-Juhani Saarinen, G Newell and Ben Marshall · 2020
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“DICE harder: a hardware implementation of the device identifier composition engine”
Lukas Jager and Richard Petri · 2020
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“A Fast and Compact RISC-V Accelerator for Ascon and Friends”
Stefan Steinegger and Robert Primas · 2020
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“Transys: Leveraging Common Security Properties Across Hardware Designs”
Rui Zhang and Cynthia Sturton · 2020
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“Efficient Hardware/Software Co-Design for Post-Quantum Crypto Algorithm SIKE on ARM and RISC-V based Microcontrollers”
Debapriya Roy, Tim Fritzmann and Georg Sigl · 2020
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“Assembly or Optimized C for Lightweight Cryptography on RISC-V?”
Campos Fabio et al · 2020
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“Guard-NoC: A Protection Against Side-Channel Attacks for MPSoCs”
Cezar Reinbrecht et al · 2020
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“Dynamic Frequency Scaling as a countermeasure against simple power analysis attack in RISC-V processors”, 2020, pp. 0
Ba-Anh Dao et al · 2020
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“Protecting Enclaves from Intra-Core Side-Channel Attacks through Physical Isolation”
Marno van Maas and Simon Moore · 2020
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“PULP-NN: accelerating quantized neural networks on parallel ultra-low-power RISC-V processors”
Angelo Garofalo et al · 2020
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“Xuantie-910: A commercial multi-core 12-stage pipeline out-of-order 64-bit high performance risc-v processor with vector extension: Industrial product”
Chen Chen et al · 2020
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“A Hardware Root-of-Trust Design for Low-Power SoC Edge Devices”
Alan Ehret, Eliakin Del, Karen Gettings and Michel Kinsy · 2020
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“Memory Protection Unit (MPU) Version 1.0” Online; accessed 14 December 2020, https://developer.arm.com/documentation/100699/0100
ARM · 2020
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“Verifying RISC-V Physical Memory Protection”, 2020
Kevin Cheang et al · 2020
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“Learn the architecture: AArch64 Exception model”, 2020
ARM · 2020
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“Em fault injection on arm and risc-v”
Mahmoud Elmohr, Haohao Liao and Catherine Gebotys · 2020
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“SeqL: Secure Scan-Locking for IP Protection”
Seetal Potluri, Aydin Aysu and Akash Kumar · 2020
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“Machine Learning Based Hardware Trojan Detection Using Electromagnetic Emanation”
Junko Takahashi et al · 2020
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“A Microprocessor Protection Architecture against Hardware Trojans in Memories”
A. Bolat et al · 2020
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“CHERI C/C++ Programming Guide”, 2020
Robert Watson et al · 2020
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“Status Report on the Second Round of the NIST Post-Quantum Cryptography Standardization Process”, 2020
Dustin Moody et al · 2020
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“Bypassing Isolated Execution on RISC-V with Fault Injection”, 2020
Shoei Nashimoto, Daisuke Suzuki, Rei Ueno and Naofumi Homma · 2020
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“RISC-V and Open Source Hardware Address New Compute Requirements” Online; accessed 7 May 2021, https://documents.westerndigital.com/content/dam/doc-library/en_us/assets/public/western-digital/collateral/tech-brief/tech-brief-western-digital-risc-v.pdf
Western Digital · 2021
Closest in time.
“SiFive Performance P550 Core Sets New Standard as Highest Performance RISC-V Processor IP” Online; accessed 24 June 2021, https://www.sifive.com/press/sifive-performance-p550-core-sets-new-standard-as-highest
SiFive · 2021
Closest in time.
“RISC-V GNU Compiler Toolchain” Online; accessed 24 June 2021, https://github.com/riscv/riscv-gnu-toolchain
The of University California(Regents) · 2021
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“Arm Architecture Reference Manual Armv8, for Armv8-A architecture profile” Online; accessed 6 May 2021, https://developer.arm.com/documentation/ddi0487/ga
ARM · 2021
Closest in time.
“Organizing The World’s Largest Hardware Security Competition: Challenges, Opportunities, and Lessons Learned”
Ahmad-Reza Sadeghi, Jeyavijayan Rajendran and Rahul Kande · 2021
Closest in time.
“Tapeout of a RISC-V crypto chip with hardware trojans: a case-study on trojan design and pre-silicon detectability”
Alexander Hepp and Georg Sigl · 2021
Closest in time.
“Risc-v bitmanip (bit manipulation) extension, document version 0.94-draft”, 2021
Claire Wolf · 2021
Closest in time.
“Cryptographic software IP protection without compromising performance or timing side-channel leakage”
Arnab Biswas · 2021
Closest in time.