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Covert channels enable information leakage across security boundaries of the operating system.
A Mathematical Theory of Communication
Claude E. Shannon. 1948 · 1948
Earlier work this paper cites.
A Note on the Confinement Problem
Butler W. Lampson. 1973 · 1973
Earlier work this paper cites.
Lattice scheduling and covert channels. In IEEE Symposium on Security and Privacy . Oakland, CA, US, 52–61
Wei-Ming Hu. 1992 · 1992
Earlier work this paper cites.
Page Placement Algorithms for Large Real-Indexed Caches
R. E. Kessler and Mark D. Hill. 1992 · 1992
Earlier work this paper cites.
Partitioned Cache Architecture as a Side-Channel Defence Mechanism
Daniel Page. 2005 · 2005
Earlier work this paper cites.
Cache missing for fun and profit
Colin Percival. 2005 · 2005
Earlier work this paper cites.
Predicting secret keys via branch prediction. In Cryptographers’ Track at the RSA Conference . Springer, 225–242
Onur Acıiçmez, Çetin Kaya Koç, and Jean-Pierre Seifert. 2007 · 2007
Earlier work this paper cites.
New Cache Designs for Thwarting Software Cache-based Side Channel Attacks. San Diego, CA, 494 – 505
Zhenghong Wang and Ruby B. Lee. 2007 · 2007
Earlier work this paper cites.
A novel cache architecture with enhanced performance and security. In 2008 41st IEEE/ACM International Symposium on Microarchitecture . 83–93
Zhenghong Wang and Ruby B. Lee. 2008 · 2008
Earlier work this paper cites.
A Tool for Estimating Information Leakage. In Computer Aided Verification , Natasha Sharygina and Helmut Veith (Eds.). Springer Berlin Heidelberg, Berlin, Heidelberg, 690–695
Tom Chothia, Yusuke Kawamoto, and Chris Novakovic. 2013 · 2013
Earlier work this paper cites.
Practical Timing Side Channel Attacks Against Kernel Space ASLR. In IEEE Symposium on Security and Privacy . San Francisco, CA, 191–205
Ralf Hund, Carsten Willems, and Thorsten Holz. 2013 · 2013
Earlier work this paper cites.
seL4: from General Purpose to a Proof of Information Flow Enforcement. In IEEE Symposium on Security and Privacy . San Francisco, CA, 415–429
Toby Murray, Daniel Matichuk, Matthew Brassil, Peter Gammie, Timothy Bourke, Sean Seefried, Corey Lewis, Xin Gao, and Gerwin Klein. 2013 · 2013
Cited alongside, same era.
CC-Hunter: Uncovering Covert Timing Channels on Shared Processor Hardware. In 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture . 216–228
J. Chen and G. Venkataramani. 2014 · 2014
Cited alongside, same era.
Comprehensive Formal Verification of an OS Microkernel
Gerwin Klein, June Andronick, Kevin Elphinstone, Toby Murray, Thomas Sewell, Rafal Kolanski, and Gernot Heiser. 2014 · 2014
Cited alongside, same era.
Thermal Covert Channels on Multi-core Platforms. In 24th USENIX Security Symposium (USENIX Security 15) . USENIX Association, Washington, D.C., 865–880
Ramya Jayaram Masti, Devendra Rai, Aanjhan Ranganathan, Christian Müller, Lothar Thiele, and Srdjan Capkun. 2015 · 2015
Cited alongside, same era.
L4 Microkernels: The Lessons from 20 Years of Research and Deployment
Time Protection: The Missing OS Abstraction. In Proceedings of the Fourteenth EuroSys Conference 2019 (Dresden, Germany) (EuroSys ’19) . ACM, New York, NY, USA, Article 1, 17 pages
Qian Ge, Yuval Yarom, Tom Chothia, and Gernot Heiser. 2019 · 2019
Later among the works it cites.
Can We Prove Time Protection?. In ACM SIGOPS Workshop on Hot Topics in Operating Systems . Bertinoro, Italy, 23–29
Gernot Heiser, Gerwin Klein, and Toby Murray. 2019 · 2019
Later among the works it cites.
POWERT Channels: A Novel Class of Covert CommunicationExploiting Power Management Vulnerabilities. In 2019 IEEE International Symposium on High Performance Computer Architecture (HPCA) . IEEE, 291–303
S Karen Khatamifard, Longfei Wang, Amitabh Das, Selcuk Kose, and Ulya R Karpuzcu. 2019 · 2019
Later among the works it cites.
Spectre Attacks: Exploiting Speculative Execution. In 40th IEEE Symposium on Security and Privacy (S&P’19)
Paul Kocher, Jann Horn, Anders Fogh, , Daniel Genkin, Daniel Gruss, Werner Haas, Mike Hamburg, Moritz Lipp, Stefan Mangard, Thomas Prescher, Michael Schwarz, and Yuval Yarom. 2019 · 2019
Later among the works it cites.
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Gernot Heiser and Kevin Elphinstone. 2016 · 2016
Cited alongside, same era.
Prefetch-guard: Leveraging hardware prefetches to defend against cache timing channels. In 2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) . 187–190
H. Fang, S. S. Dayapule, F. Yao, M. Doroslovački, and G. Venkataramani. 2018 · 2018
Cited alongside, same era.
A Survey of Microarchitectural Timing Attacks and Countermeasures on Contemporary Hardware
Qian Ge, Yuval Yarom, David Cock, and Gernot Heiser. 2018b · 2018
Cited alongside, same era.
Processor Hardware Security Vulnerabilities and their Detection by Unique Program Execution Checking. In 2019 Design, Automation Test in Europe Conference Exhibition (DATE) . 994–999
M. R. Fadiheh, D. Stoffel, C. Barrett, S. Mitra, and W. Kunz. 2019 · 2019
Cited alongside, same era.
PrODACT: Prefetch-Obfuscator to Defend Against Cache Timing Channels
Hongyu Fang, Sai Santosh Dayapule, Fan Yao, Miloš Doroslovački, and Guru Venkataramani. 2019 · 2019
Cited alongside, same era.
Principled Elimination of Microarchitectural Timing Channels through Operating-System Enforced Time Protection
Qian Ge. 2019 · 2019
Cited alongside, same era.
No Security Without Time Protection: We Need a New Hardware-Software Contract. In Proceedings of the 9th Asia-Pacific Workshop on Systems (Jeju Island, Republic of Korea) (APSys ’18) . ACM, New York, NY, USA, Article 1, 9 pages
Qian Ge, Yuval Yarom, and Gernot Heiser. 2018a
Cited in the paper.
Memory Subsystem for the First Fully Open-Source RISC-V Heterogeneous SoC
Wolfgang Rönninger. 2019 · 2019
Later among the works it cites.
The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology
F. Zaruba and L. Benini. 2019 · 2019
Later among the works it cites.
Timing Channel Benchmarking Tool
Qian Ge. 2015 · 2020
Closest in time.
seL4 Benchmarking Applications and Support Library
Anna Lyons. 2014 · 2020
Closest in time.
The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
Andrew Waterman and Krste Asanović. 2019 · 2020
Closest in time.
Mastik: A Micro-Architectural Side-Channel Toolkit
Yuval Yarom. 2016 · 2020
Closest in time.