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FPGA-based accelerators of deep learning networks for learning and classification: A review
A. Shawahna, et al · 1901
Earlier work this paper cites.
Z. Dong, et al · 1905
Earlier work this paper cites.
NeckSense: A multi-sensor necklace for detecting eating activities in free-living conditions
S. Zhang, et al · 1911
Earlier work this paper cites.
A flexible FPGA accelerator for convolutional neural networks. (2019)
K. Majumder et al · 1912
Earlier work this paper cites.
Optimal brain damage. In Advances in Neural Information Processing Systems , D. S. Touretzky (Ed.), Vol. 2. Morgan-Kaufmann, 598
Y. LeCun, et al · 1990
Earlier work this paper cites.
Fast inference of boosted decision trees in FPGAs for particle physics
S. Summers et al · 2002
Earlier work this paper cites.
Benchmarking TinyML Systems: Challenges and Direction. (2020)
C. R. Banbury, et al · 2003
Earlier work this paper cites.
Compressing deep neural networks on FPGAs to binary and ternary precision with hls4ml
J. Ngadiuba, et al · 2003
Earlier work this paper cites.
A. Renda, et al · 2003
Earlier work this paper cites.
Feature selection, L1 vs. L2 regularization, and rotational invariance. In 21st International Conference On Machine Learning (ICML ’04) . ACM, New York, NY, USA, 78
A. Y. Ng. 2004 · 2004
Earlier work this paper cites.
C. N. Coelho, et al · 2006
Earlier work this paper cites.
Measuring the gap between FPGAs and ASICs
I. Kuon et al · 2006
Earlier work this paper cites.
Y. Iiyama et al · 2008
Earlier work this paper cites.
Rectified linear units improve restricted Boltzmann machines. In 27th International Conference on International Conference on Machine Learning (ICML’10) . Omnipress, Madison, WI, USA, 807
V. Nair et al · 2010
Earlier work this paper cites.
MNIST handwritten digit database
Y. LeCun et al · 2010
Earlier work this paper cites.
D. S. Rankin, et al · 2010
Earlier work this paper cites.
Torch7: A Matlab-like environment for machine learning. In BigLearn, NIPS Workshop
R. Collobert, et al · 2011
Earlier work this paper cites.
Deep sparse rectifier neural networks. In 14th International Conference on Artificial Intelligence and Statistics , G. Gordon, et al
X. Glorot, et al · 2011
Earlier work this paper cites.
Improving the speed of neural networks on CPUs. In Deep Learning and Unsupervised Feature Learning Workshop at the 25th Conference on Neural Information Processing Systems
V. Vanhoucke, et al · 2011
Earlier work this paper cites.
S.-E. Chang, et al · 2012
Earlier work this paper cites.
1.1 Computing’s energy problem (and what we can do about it). In 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) . IEEE, 10
M. Horowitz. 2014 · 2014
Earlier work this paper cites.
Y. Jia, et al · 2014
Earlier work this paper cites.
Compressing deep convolutional networks using vector quantization. (2014)
Y. Gong, et al · 2014
Earlier work this paper cites.
A survey and evaluation of FPGA high-level synthesis tools
R. Nane, et al · 2015
Earlier work this paper cites.
TensorFlow: Large-Scale Machine Learning on Heterogeneous Systems
M. Abadi, et al · 2015
Earlier work this paper cites.
S. Ioffe et al · 2015
Earlier work this paper cites.
S. Gupta, et al · 2015
Earlier work this paper cites.
M. Courbariaux, et al · 2015
Cited alongside, same era.
S. Han, et al · 2015
Cited alongside, same era.
fpgaConvNet: A framework for mapping convolutional neural networks on FPGAs. In 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) . IEEE, 40
S. I. Venieris et al · 2016
Cited alongside, same era.
From high-level deep neural models to FPGAs. In 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) . IEEE, 1
H. Sharma, et al · 2016
Cited alongside, same era.
The importance of calorimetry for highly-boosted jet substructure
E. Coleman, et al · 2018
Later among the works it cites.
Quantized neural networks: Training neural networks with low precision weights and activations
I. Hubara, et al · 2018
Later among the works it cites.
C. Louizos, et al · 2018
Later among the works it cites.
UNIQ: Uniform noise injection for the quantization of neural networks. (2018)
C. Baskin, et al · 2018
Later among the works it cites.
7 Series DSP48E1 slice user guide
Xilinx. 2018 · 2018
alphaXiv searches the wider corpus for related work and actual follow-ups.
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R. DiCecco, et al · 2016
Cited alongside, same era.
Efficient FPGA acceleration of convolutional neural networks using logical-3D compute array. In 2016 Design, Automation Test in Europe Conference Exhibition (DATE) . IEEE, 1393
A. Rahman, et al · 2016
Cited alongside, same era.
J. Wu, et al · 2016
Cited alongside, same era.
S. Han, et al · 2016
Cited alongside, same era.
Binarized neural networks. In Advances in Neural Information Processing Systems , D. D. Lee, et al
I. Hubara, et al · 2016
Cited alongside, same era.
M. Rastegari, et al · 2016
Cited alongside, same era.
Deep neural networks are robust to weight binarization and other non-linear distortions. (2016)
P. Merolla, et al · 2016
Cited alongside, same era.
Ternary weight networks. (2016)
F. Li et al · 2016
Cited alongside, same era.
Later among the works it cites.
A modular digital VLSI flow for high-productivity SoC design. In ACM/ESDA/IEEE Design Automation Conference (DAC) . IEEE, 1
B. Khailany, et al · 2018
Later among the works it cites.
A survey of FPGA-based neural network inference accelerators
K. Guo, et al · 2019
Later among the works it cites.
P. N. Whatmough, et al · 2019
Later among the works it cites.
ARM-software/DeepFreeze
P. N. Whatmough et al · 2019
Later among the works it cites.
K. Wang, et al · 2019
Later among the works it cites.
J. Frankle et al · 2019
Later among the works it cites.
Xilinx/brevitas: bnn_pynq-r1
Alessandro, et al · 2020
Later among the works it cites.
TensorFlow Lite
Google. 2020 · 2020
Later among the works it cites.
G. B. Hacene, et al · 2020
Later among the works it cites.
Towards automatic high-level code deployment on reconfigurable platforms: A survey of high-level synthesis tools and toolchains
M. W. Numan, et al · 2020
Later among the works it cites.
Intel high level synthesis compiler
Intel. 2020 · 2020
Later among the works it cites.
Model compression and hardware acceleration for neural networks: A comprehensive survey
L. Deng, et al · 2020
Later among the works it cites.
A comprehensive survey on model compression and acceleration
T. Choudhary, et al · 2020
Later among the works it cites.
D. Blalock, et al · 2020
Later among the works it cites.
Design of a reconfigurable autoencoder algorithm for detector front-end ASICs. In IEEE Nuclear Science Symposium & Medical Imaging Conference . IEEE
C. Herwig, et al · 2020
Later among the works it cites.
High-level synthesis to on-chip implementation of a reconfigurable AI accelerator for front-end data analysis at the HL-LHC. In IEEE Nuclear Science Symposium & Medical Imaging Conference . IEEE
F. Fahim, et al · 2020
Later among the works it cites.
fastmachinelearning/hls4ml: bartsia (v0.5.0)
V. Loncar et al · 2021
Closest in time.
Fast convolutional neural networks on FPGAs with hls4ml
T. Aarrestad, et al · 2021
Closest in time.
Ps and Qs: Quantization-aware pruning for efficient low latency neural network inference. (2021)
B. Hawks, et al · 2021
Closest in time.
Xilinx/Vitis-AI
Xilinx. 2021 · 2021
Closest in time.
Xilinx/finn
Y. Umuroglu et al · 2021
Closest in time.
mlcommons/tiny
N. Jeffries et al · 2021
Closest in time.