Compressing deep neural networks on FPGAs to binary and ternary precision with HLS4ML

Understand

We present the implementation of binary and ternary neural networks in the hls4ml library, designed to automatically convert deep neural network models to digital circuits with FPGA firmware.

• Starting from benchmark models trained with floating point precision, we investigate different strategies to reduce the network's resource consumption by reducing the numerical precision of the network parameters to binary or ternary.
• We discuss the trade-off between model accuracy and resource consumption.
• In addition, we show how to balance between latency and accuracy by retaining full precision on a selected subset of network components.