Fetching the paper…
Reading the bibliography…
Cyber attacks and malware are now more prevalent than ever and the trend is ever upward.
L. Yuan, W. Xing, H. Chen, and B. Zang, “Security breaches as pmu deviation: detecting and identifying security attacks using performance counters,” in Proceedings of the Second Asia-Pacific Workshop on Systems . ACM, 2011, p. 6
2011
Earlier work this paper cites.
R. Martin, J. Demme, and S. Sethumadhavan, “Timewarp: rethinking timekeeping and performance monitoring mechanisms to mitigate side-channel attacks,” ACM SIGARCH Computer Architecture News , vol. 40, no. 3, pp. 118–129, 2012
2012
Earlier work this paper cites.
Y. Zhang, A. Juels, M. K. Reiter, and T. Ristenpart, “Cross-vm side channels and their use to extract private keys,” in Proceedings of the 2012 ACM conference on Computer and communications security . ACM, 2012, pp. 305–316
2012
Earlier work this paper cites.
J. Demme, M. Maycock, J. Schmitz, A. Tang, A. Waksman, S. Sethumadhavan, and S. Stolfo, “On the feasibility of online malware detection with performance counters,” in ACM SIGARCH Computer Architecture News , vol. 41, no. 3. ACM, 2013, pp. 559–570
2013
Earlier work this paper cites.
V. Pappas, M. Polychronakis, and A. D. Keromytis, “Transparent rop exploit mitigation using indirect branch tracing.” in USENIX Security , vol. 30, 2013, p. 38
2013
Earlier work this paper cites.
M. Kayaalp, T. Schmitt, J. Nomani, D. Ponomarev, and N. Abu-Ghazaleh, “Scrap: Architecture for signature-based protection from code reuse attacks,” in High Performance Computer Architecture (HPCA2013), 2013 IEEE 19th International Symposium on . IEEE, 2013, pp. 258–269
2013
Earlier work this paper cites.
J. R. and I. Corporation, “Processor tracing,” https://software.intel.com/en-us/blogs/2013/09/18/processor-tracing , 2013, [Online; published 18-September-2013]
2013
Earlier work this paper cites.
S. Bhunia, M. S. Hsiao, M. Banga, and S. Narasimhan, “Hardware trojan attacks: threat analysis and countermeasures,” Proceedings of the IEEE , vol. 102, no. 8, pp. 1229–1247, 2014
2014
Earlier work this paper cites.
Y. Yarom and K. Falkner, “FLUSH+RELOAD: A High Resolution, Low Noise, L3 Cache Side-Channel Attack.” in USENIX Security , vol. 2014, 2014, pp. 719–732
2014
Earlier work this paper cites.
Y. Cheng, Z. Zhou, Y. Miao, X. Ding, H. DENG et al. , “Ropecker: A generic and practical approach for defending against rop attack,” Proceedings of the 21th Annual Network and Distributed System Security Symposium (NDSSÕ14) , 2014
2014
Earlier work this paper cites.
C. Liu, C. Yang, and Y. Shen, “Leveraging microarchitectural side channel information to efficiently enhance program control flow integrity,” in Hardware/Software Codesign and System Synthesis (CODES+ ISSS), 2014 International Conference on . IEEE, 2014, pp. 1–9
2014
Cited alongside, same era.
M. B. Bahador, M. Abadi, and A. Tajoddin, “Hpcmalhunter: Behavioral malware detection using hardware performance counters and singular value decomposition,” in Computer and Knowledge Engineering (ICCKE), 2014 4th International eConference on . IEEE, 2014, pp. 703–708
2014
Cited alongside, same era.
2015
Cited alongside, same era.
X. Wang, C. Konstantinou, M. Maniatakos, and R. Karri, “Confirm: Detecting firmware modifications in embedded systems using hardware performance counters,” in Computer-Aided Design (ICCAD), 2015 IEEE/ACM International Conference on . IEEE, 2015, pp. 544–551
Z. B. Aweke, S. F. Yitbarek, R. Qiao, R. Das, M. Hicks, Y. Oren, and T. Austin, “Anvil: Software-based protection against next-generation rowhammer attacks,” ACM SIGPLAN Notices , vol. 51, no. 4, pp. 743–755, 2016
2016
Later among the works it cites.
G. Torres and C. Liu, “Can data-only exploits be detected at runtime using hardware events?: A case study of the heartbleed vulnerability,” in Proceedings of the Hardware and Architectural Support for Security and Privacy 2016 . ACM, 2016, p. 2
2016
Later among the works it cites.
V. Jyothi, X. Wang, S. K. Addepalli, and R. Karri, “Brain: Behavior based adaptive intrusion detection in networks: Using hardware performance counters to detect ddos attacks,” in VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), 2016 29th International Conference on . IEEE, 2016, pp. 587–588
2016
Later among the works it cites.
alphaXiv searches the wider corpus for related work and actual follow-ups.
alphaXiv is searching for related work…
2015
Cited alongside, same era.
J. Nomani and J. Szefer, “Predicting program phases and defending against side-channel attacks using hardware performance counters,” in Proceedings of the Fourth Workshop on Hardware and Architectural Support for Security and Privacy . ACM, 2015, p. 9
2015
Cited alongside, same era.
Q. Ge, Y. Yarom, D. Cock, and G. Heiser, “A survey of microarchitectural timing attacks and countermeasures on contemporary hardware,” Journal of Cryptographic Engineering , pp. 1–27, 2016
2016
Cited alongside, same era.
“Intel 64 and ia-32 architectures software developerÕs manual volume 3, chapter 17, 18, and 19,” 2016
2016
Cited alongside, same era.
2016
Cited alongside, same era.
X. Wang, C. Konstantinou, M. Maniatakos, R. Karri, S. Lee, P. Robison, P. Stergiou, and S. Kim, “Malicious firmware detection with hardware performance counters,” IEEE Transactions on Multi-Scale Computing Systems , vol. 2, no. 3, pp. 160–173, 2016
2016
Cited alongside, same era.
M. Chiappetta, E. Savas, and C. Yilmaz, “Real time detection of cache-based side-channel attacks using hardware performance counters,” Applied Soft Computing , vol. 49, pp. 1162–1174, 2016
2016
Cited alongside, same era.
2017
Later among the works it cites.
2017
Later among the works it cites.
M. Alam, S. Bhattacharya, D. Mukhopadhyay, and S. Bhattacharya, “Performance counters to rescue: A machine learning based safeguard against micro-architectural side-channel-attacks,” IACR Cryptology ePrint Archive , 2017
2017
Later among the works it cites.
Y. Liu, P. Shi, X. Wang, H. Chen, B. Zang, and H. Guan, “Transparent and efficient cfi enforcement with intel processor trace,” in High Performance Computer Architecture (HPCA), 2017 IEEE International Symposium on . IEEE, 2017, pp. 529–540
2017
Later among the works it cites.
W. contributors, “Support vector machine — wikipedia, the free encyclopedia,” https://en.wikipedia.org/w/index.php?title=Support_vector_machine&oldid=826949511 , 2018, [Online; accessed 25-February-2018]
2018
Closest in time.
W. contributors, “Dynamic time warping — wikipedia, the free encyclopedia,” https://en.wikipedia.org/w/index.php?title=Dynamic_time_warping&oldid=822466906 , 2018, [Online; accessed 25-February-2018]
2018
Closest in time.