RSA key extraction via low-bandwidth acoustic cryptanalysis
2014
Cited alongside, same era.
Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors, 2014
2014
Cited alongside, same era.
FLUSH+RELOAD: A high resolution, low noise, L3 cache side-channel attack
2014
Cited alongside, same era.
Flush+Reload
2014
Cited alongside, same era.
On subnormal floating point and abnormal timing
2015
Cited alongside, same era.
Cache template attacks: Automating attacks on inclusive last-level caches
2015
Cited alongside, same era.
Last-level cache side-channel attacks are practical
2015
Cited alongside, same era.
Mapping the Intel last-level cache
2015
Cited alongside, same era.
https://www.amd.com/en-us/press-releases/Pages/amd-takes-computing-2016dec13.aspx
AMD takes computing to a new horizon with Ryzen processors, 2016 · 2016
Cited alongside, same era.
Intel 64 and IA-32 architectures software developer manual, vol 3: System programmer’s guide, section 8.3, 2016
2016
Cited alongside, same era.
Jump over ASLR: attacking branch predictors to bypass ASLR
2016
Cited alongside, same era.
A survey of microarchitectural timing attacks and countermeasures on contemporary hardware
2016
Cited alongside, same era.