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Timing channels are information flows, encoded in the relative timing of events, that bypass the system's protection mechanisms.
A note on the confinement problem
Butler W. Lampson · 1973
Earlier work this paper cites.
A comment on the confinement problem
Steven. B. Lipner · 1975
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Program confinement in KVM/370
Marvin Schaefer, Barry Gold, Richard Linde, and John Scheid · 1977
Earlier work this paper cites.
Formal models for computer security
Carl E. Landwehr · 1981
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Design and verification of secure systems
John Rushby · 1981
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A trusted computing base for embedded systems
John Rushby · 1984
Earlier work this paper cites.
Trusted Computer System Evaluation Criteria
DoD · 1986
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Page placement algorithms for large real-indexed caches
R. E. Kessler and Mark D. Hill · 1992
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OS-controlled cache predictability for real-time systems
Jochen Liedtke, Hermann Härtig, and Michael Hohmuth · 1997
Earlier work this paper cites.
A mathematical theory of communication
Claude E. Shannon · 2001
Earlier work this paper cites.
Microbenchmarks for determining branch predictor organization
Milena Milenkovic, Aleksandar Milenkovic, and Jeffrey Kulick · 2004
Earlier work this paper cites.
Cache-timing attacks on AES, 2005
Daniel J. Bernstein · 2005
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Cache missing for fun and profit
Colin Percival · 2005
Earlier work this paper cites.
Cache attacks and countermeasures: The case of AES
Dag Arne Osvik, Adi Shamir, and Eran Tromer · 2006
Earlier work this paper cites.
Yet another microarchitectural attack: exploiting I-cache
Onur Acıiçmez · 2007
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Cheap hardware parallelism implies cheap security
Onur Acıiçmez and Jean-Pierre Seifert · 2007
Earlier work this paper cites.
U.S. Government Protection Profile for Separation Kernels in Environments Requiring High Robustness
IAD · 2007
Earlier work this paper cites.
A vulnerability in RSA implementations due to instruction cache analysis and its demonstration on OpenSSL
Onur Acıiçmez and Werner Schindler · 2008
Cited alongside, same era.
New results on instruction cache attacks
Onur Acıiçmez, Billy Bob Brumley, and Philipp Grabher · 2010
Cited alongside, same era.
Predictive black-box mitigation of timing channels
Aslan Askarov, Danfeng Zhang, and Andrew C. Myers · 2010
Cited alongside, same era.
Limiting cache-based side-channel in multi-tenant cloud using dynamic page coloring
Jicheng Shi, Xiang Song, Haibo Chen, and Binyu Zang · 2011
Cited alongside, same era.
The security impact of a new cryptographic library
Daniel J. Bernstein, Tanja Lange, and Peter Schwabe · 2012
Cited alongside, same era.
Whispers in the hyper-space: High-speed covert channel attacks in the cloud
Zhenyu Wu, Zhang Xu, and Haining Wang · 2012
Robust and efficient elimination of cache and timing side channels
Benjamin A. Braun, Suman Jana, and Dan Boneh · 2015
Later among the works it cites.
Last-level cache side-channel attacks are practical
Fangfei Liu, Yuval Yarom, Qian Ge, Gernot Heiser, and Ruby B Lee · 2015
Later among the works it cites.
Reverse engineering Intel last-level cache complex addressing using performance counters
Clémentine Maurice, Nicolas Le Scouarnec, Christoph Neumann, Olivier Heen, and Aurélien Francillon · 2015
Later among the works it cites.
Reverse engineering Intel DRAM addressing and exploitation
Peter Pessl, Daniel Gruss, Clémentine Maurice, Michael Schwarz, and Stefan Mangard · 2015
Later among the works it cites.
Mapping the Intel last-level cache
Yuval Yarom, Qian Ge, Fangfei Liu, Ruby B. Lee, and Gernot Heiser · 2015
Later among the works it cites.
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Cited alongside, same era.
A server-side solution to cache-based side-channel attacks in the cloud
Michael Godfrey and Mohammad Zulkernine · 2013
Cited alongside, same era.
Practical timing side channel attacks against kernel space ASLR
Ralf Hund, Carsten Willems, and Thorsten Holz · 2013
Cited alongside, same era.
seL4: from general purpose to a proof of information flow enforcement
Toby Murray, Daniel Matichuk, Matthew Brassil, Peter Gammie, Timothy Bourke, Sean Seefried, Corey Lewis, Xin Gao, and Gerwin Klein · 2013
Cited alongside, same era.
Intel Ivy Bridge cache replacement policy
Henry Wong · 2013
Cited alongside, same era.
Düppel: Retrofitting commodity operating systems to mitigate cache side channels in the cloud
Yinqian Zhang and Michael K. Reiter · 2013
Cited alongside, same era.
The last mile: An empirical study of some timing channels on seL4
David Cock, Qian Ge, Toby Murray, and Gernot Heiser · 2014
Cited alongside, same era.
Covert channels through random number generator: Mechanisms, capacity estimation and mitigations
Dmitry Evtyushkin and Dmitry Ponomarev · 2016
Closest in time.
Jump over ASLR: Attacking branch predictors to bypass ASLR
Dmitry Evtyushkin, Dmitry Ponomarev, and Nael Abu-Ghazaleh · 2016
Closest in time.
The BTB in contemporary Intel chips
Matt Godbolt · 2016
Closest in time.
Cache storage channels: Alias-driven attacks and verified countermeasures
Roberto Guanciale, Hamed Nemati, Christoph Baumann, and Mads Dam · 2016
Closest in time.
Intel 64 and IA-32 Architecture Software Developer’s Manual Volume 2: Instruction Set Reference, A-Z
Intel 64 & IA-32 ASDM · 2016
Closest in time.
ARMageddon: Cache attacks on mobile devices
Moritz Lipp, Daniel Gruss, Raphael Spreitzer, Clémentine Maurice, and Stefan Mangard · 2016
Closest in time.
DRAMA: Exploiting DRAM addressing for cross-CPU attacks
Peter Pessl, Daniel Gruss, Clémentine Maurice, Michael Schwarz, and Stefan Mangard · 2016
Closest in time.
Mastik: A micro-architectural side-channel toolkit
Yuval Yarom · 2016
Closest in time.
CacheBleed: A timing attack on OpenSSL constant time RSA
Yuval Yarom, Daniel Genkin, and Nadia Heninger · 2016
Closest in time.
A survey of microarchitectural timing attacks and countermeasures on contemporary hardware
Qian Ge, Yuval Yarom, David Cock, and Gernot Heiser · 2017
Closest in time.
Hello from the other side: SSH over robust cache covert channels in the cloud
Clémentine Maurice, Manuel Weber, Michael Schwartz, Lukas Giner, Daniel Gruss, Carlo Alberto Boano, Kay Römer, and Stefan Mangard · 2017
Closest in time.