A Survey of Neuromorphic Computing and Neural Networks in Hardware

E. Gale, B. D. L. Costello, and A. Adamatzky, “Observation and characterization of memristor current spikes and their application to neuromorphic computation,” in NUMERICAL ANALYSIS AND APPLIED MATHEMATICS ICNAAM 2012: International Conference of Numerical Analysis and Applied Mathematics , vol. 1479, no. 1. AIP Publishing, 2012, pp. 1898–1901

1901

Earlier work this paper cites.

A. G. Andreou and T. G. Edwards, “Analog vlsi neuromorphic processing: case study of a multiple-target-tracking system,” in Neural Networks, 1994. IEEE World Congress on Computational Intelligence., 1994 IEEE International Conference on , vol. 3. IEEE, 1994, pp. 1903–1906

1906

Earlier work this paper cites.

T. Duong, S. Kemeny, M. Tran, T. Daud, A. Thakoor, D. Ludwig, C. Saunders, and J. Carson, “Low power analog neurosynapse chips for a 3-d ?sugarcube? neuroprocessor,” in Neural Networks, 1994. IEEE World Congress on Computational Intelligence., 1994 IEEE International Conference on , vol. 3. IEEE, 1994, pp. 1907–1911

1911

Earlier work this paper cites.

K. Nakada, T. Asai, T. Hirose, and Y. Amemiya, “Analog cmos implementation of a neuromorphic oscillator with current-mode low-pass filters,” in Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on . IEEE, 2005, pp. 1923–1926

1926

Earlier work this paper cites.

S. Saïghi, J. Tomas, Y. Bornat, B. Belhadj, O. Malot, and S. Renaud, “Real-time multi-board architecture for analog spiking neural networks,” in Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on . IEEE, 2010, pp. 1939–1942

1942

Earlier work this paper cites.

W. S. McCulloch and W. Pitts, “A logical calculus of the ideas immanent in nervous activity,” The bulletin of mathematical biophysics , vol. 5, no. 4, pp. 115–133, 1943

1943

Earlier work this paper cites.

A. M. Turing, “Computing machinery and intelligence,” Mind , vol. 59, no. 236, pp. 433–460, 1950

1950

Earlier work this paper cites.

J. Schemmel, D. Bruderle, A. Grubl, M. Hock, K. Meier, and S. Millner, “A wafer-scale neuromorphic hardware system for large-scale neural modeling,” in Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on . IEEE, 2010, pp. 1947–1950

1950

Earlier work this paper cites.

A. L. Hodgkin and A. F. Huxley, “A quantitative description of membrane current and its application to conduction and excitation in nerve,” The Journal of physiology , vol. 117, no. 4, p. 500, 1952

1952

Earlier work this paper cites.

G. Indiveri, F. Stefanini, and E. Chicca, “Spike-based learning with a generalized integrate and fire silicon neuron,” in Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on . IEEE, 2010, pp. 1951–1954

1954

Earlier work this paper cites.

Y. Sato, K. Shibata, M. Asai, M. Ohki, M. Sugie, T. Sakaguchi, M. Hashimoto, and Y. Kuwabara, “Development of a high-performance general purpose neuro-computer composed of 512 digital neurons,” in Neural Networks, 1993. IJCNN’93-Nagoya. Proceedings of 1993 International Joint Conference on , vol. 2. IEEE, 1993, pp. 1967–1970

1970

Earlier work this paper cites.

L. Chua, “Memristor-the missing circuit element,” IEEE Transactions on circuit theory , vol. 18, no. 5, pp. 507–519, 1971

1971

Earlier work this paper cites.

J. Backus, “Can programming be liberated from the von neumann style?: a functional style and its algebra of programs,” Communications of the ACM , vol. 21, no. 8, pp. 613–641, 1978

1978

Earlier work this paper cites.

D. B. Mundie and L. W. Massengill, “A simulation and training technique for analog neural network implementations,” in Neural Networks, 1994. IEEE World Congress on Computational Intelligence., 1994 IEEE International Conference on , vol. 3. IEEE, 1994, pp. 1975–1980

1980

Earlier work this paper cites.

M. Duranton and J. Sirat, “Learning on vlsi: A general purpose digital neurochip,” in Neural Networks, 1989. IJCNN., International Joint Conference on . IEEE, 1986, pp. 613–vol

1986

Earlier work this paper cites.

D. Tank and J. J. Hopfield, “Simple’neural’optimization networks: An a/d converter, signal decision circuit, and a linear programming circuit,” Circuits and Systems, IEEE Transactions on , vol. 33, no. 5, pp. 533–541, 1986

1986

Earlier work this paper cites.

Y. Tsividis and D. Anastassiou, “Switched-capacitor neural networks,” Electronics Letters , vol. 23, no. 18, pp. 958–959, 1987

1987

Earlier work this paper cites.

L. D. Jackel, H. Graf, and R. Howard, “Electronic neural network chips,” Applied optics , vol. 26, no. 23, pp. 5077–5080, 1987

1987

Earlier work this paper cites.

R. E. Howard, D. B. Schwartz, J. S. Denker, R. W. Epworth, H. P. Graf, W. E. Hubbard, L. D. Jackel, B. L. Straughn, and D. Tennant, “An associative memory based on an electronic neural network architecture,” Electron Devices, IEEE Transactions on , vol. 34, no. 7, pp. 1553–1556, 1987

1987

Earlier work this paper cites.

H. Graf and P. De Vegvar, “A cmos associative memory chip based on neural networks,” in Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International , vol. 30. IEEE, 1987, pp. 304–305

1987

Earlier work this paper cites.

Y. Tsividis and S. Satyanarayana, “Analogue circuits for variable-synapse electronic neural networks,” Electronics Letters , vol. 23, no. 24, pp. 1313–1314, 1987

1987

Earlier work this paper cites.

A. F. Murray and A. V. Smith, “A novel computational and signalling method for vlsi neural networks,” in Solid-state Circuits Conference, 1987. ESSCIRC’87. 13th European . IEEE, 1987, pp. 19–22

1987

Earlier work this paper cites.

H. P. Graf, L. D. Jackel, and W. E. Hubbard, “A cmos implementation of a neural net-work model,” in Advanced Research in VLSI, Proc. StanfordConf . Citeseer, 1987

1987

Earlier work this paper cites.

A. F. Murray and A. V. Smith, “Asynchronous vlsi neural networks using pulse-stream arithmetic,” Solid-State Circuits, IEEE Journal of , vol. 23, no. 3, pp. 688–697, 1988

1988

Earlier work this paper cites.

U. Koch and M. Brunner, “A modular analog neuron-model for research and teaching,” Biological cybernetics , vol. 59, no. 4-5, pp. 303–312, 1988

1988

Earlier work this paper cites.

S. Aunet, B. Oelmann, S. Abdalla, and Y. Berg, “Reconfigurable subthreshold cmos perceptron,” in Neural Networks, 2004. Proceedings. 2004 IEEE International Joint Conference on , vol. 3. IEEE, 2004, pp. 1983–1988

1988

Earlier work this paper cites.

D. E. Rumelhart, G. E. Hinton, and R. J. Williams, “Learning representations by back-propagating errors,” Cognitive modeling , vol. 5, no. 3, p. 1, 1988

1988

Earlier work this paper cites.

B. Furman and A. Abidi, “An analog cmos backward error-propagation lsi,” in Signals, Systems and Computers, 1988. Twenty-Second Asilomar Conference on , vol. 2. IEEE, 1988, pp. 645–648

1988

Earlier work this paper cites.

P. Houselander, J. Taylor, and D. Haigh, “A current mode analogue circuit for implementing artificial neural networks,” in Electronic Filters, IEE 1988 Saraga Colloquium on . IET, 1988, pp. 14–1

1988

Earlier work this paper cites.

M. Walker and L. Akers, “A neuromorphic approach to adaptive digital circuitry,” in Computers and Communications, 1988. Conference Proceedings., Seventh Annual International Phoenix Conference on . IEEE, 1988, pp. 19–23

1988

Earlier work this paper cites.

J. J. Paulos and P. W. Hollis, “Neural networks using analog multipliers,” in Circuits and Systems, 1988., IEEE International Symposium on . IEEE, 1988, pp. 499–502

1988

Earlier work this paper cites.

H. P. Graf, L. D. Jackel, and W. E. Hubbard, “Vlsi implementation of a neural network model,” Computer , vol. 21, no. 3, pp. 41–49, 1988

1988

Earlier work this paper cites.

U. Ruckert and K. Goser, “Vlsi architectures for associative networks,” in Circuits and Systems, 1988., IEEE International Symposium on . IEEE, 1988, pp. 755–758

1988

Earlier work this paper cites.

J. Mann, R. Lippmann, B. Berger, and J. Raffel, “A self-organizing neural net chip,” in Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988 . IEEE, 1988, pp. 10–3

1988

Earlier work this paper cites.

L. O. Chua and L. Yang, “Cellular neural networks: Applications,” IEEE Transactions on circuits and systems , vol. 35, no. 10, pp. 1273–1290, 1988

1988

Earlier work this paper cites.

A. Rodríguez-Vázquez, A. Rueda, J. L. Huertas, and R. Dominguez-Castro, “Switched-capacitor neural networks for linear programming,” Electronics Letters , vol. 24, no. 8, pp. 496–498, 1988

1988

Earlier work this paper cites.

F. Blayo and P. Hurat, “A vlsi systolic array dedicated to hopfield neural network,” in VLSI for Artificial Intelligence . Springer, 1989, pp. 255–264

1989

Earlier work this paper cites.

F. Salam, “A model of neural circuits for programmable vlsi implementation,” in Circuits and Systems, 1989., IEEE International Symposium on . IEEE, 1989, pp. 849–851

1989

Earlier work this paper cites.

L. Akers, M. Walker, D. Ferry, and R. Grondin, “A limited-interconnect, highly layered synthetic neural architecture,” in VLSI for artificial intelligence . Springer, 1989, pp. 218–226

1989

Earlier work this paper cites.

J. L. Meador and C. S. Cole, “A low-power cmos circuit which emulates temporal electrical properties of neurons,” in Advances in neural information processing systems , 1989, pp. 678–686

1989

Earlier work this paper cites.

D. Myers and R. Hutchinson, “Efficient implementation of piecewise linear activation function for digital vlsi neural networks,” Electronics Letters , vol. 25, p. 1662, 1989

1989

Earlier work this paper cites.

H. Card and W. Moore, “Implementation of plasticity in mos synapses,” in Artificial Neural Networks, 1989., First IEE International Conference on (Conf. Publ. No. 313) . IET, 1989, pp. 33–36

1989

Earlier work this paper cites.

S. Bibyk and M. Ismail, “Issues in analog vlsi and mos techniques for neural computing,” in Analog VLSI Implementation of Neural systems . Springer, 1989, pp. 103–133

1989

Earlier work this paper cites.

S. Eberhardt, T. Duong, and A. Thakoor, “Design of parallel hardware neural network systems from custom analog vlsi’building block’chips,” in Neural Networks, 1989. IJCNN., International Joint Conference on . IEEE, 1989, pp. 183–190

1989

Earlier work this paper cites.

S. Satyanarayana, Y. Tsividis, and H. Graf, “Analogue neural networks with distributed neurons,” Electronics Letters , vol. 25, no. 5, pp. 302–304, 1989

1989

Earlier work this paper cites.

R. Shimabukuro, P. Shoemaker, and M. Stewart, “Circuitry for artificial neural networks with non-volatile analog memories,” in Circuits and Systems, 1989., IEEE International Symposium on . IEEE, 1989, pp. 1217–1220

1989

Earlier work this paper cites.

M. Walker, P. Hasler, and L. Akers, “A cmos neural network for pattern association,” IEEE Micro , no. 5, pp. 68–74, 1989

1989

Earlier work this paper cites.

S. Kung and J. Hwang, “Digital vlsi architectures for neural networks,” in Circuits and Systems, 1989., IEEE International Symposium on . IEEE, 1989, pp. 445–448

1989

Earlier work this paper cites.

D. Myers and G. Brebner, “The implementation of hardware neural net systems,” in Artificial Neural Networks, 1989., First IEE International Conference on (Conf. Publ. No. 313) . IET, 1989, pp. 57–61

1989

Earlier work this paper cites.

M. Duranton and N. Mauduit, “A general purpose digital architecture for neural network simulations,” in Artificial Neural Networks, 1989., First IEE International Conference on (Conf. Publ. No. 313) . IET, 1989, pp. 62–66

1989

Earlier work this paper cites.

F. Salam, N. Khachab, M. Ismail, and Y. Wang, “An analog mos implementation of the synaptic weights for feedback neural nets,” in Circuits and Systems, 1989., IEEE International Symposium on . IEEE, 1989, pp. 1223–1226

1989

Earlier work this paper cites.

N. I. Khachab and M. Ismail, “A new continuous-time mos implementation of feedback neural networks,” in Circuits and Systems, 1989., Proceedings of the 32nd Midwest Symposium on . IEEE, 1989, pp. 221–224

1989

Earlier work this paper cites.

M. Verleysen, B. Sirletti, A. M. Vandemeulebroecke, and P. G. Jespers, “Neural networks for high-storage content-addressable memory: Vlsi circuit and learning algorithm,” Solid-State Circuits, IEEE Journal of , vol. 24, no. 3, pp. 562–569, 1989

1989

Earlier work this paper cites.

F. Blayo and P. Hurat, “A reconfigurable wsi neural network,” in Wafer Scale Integration, 1989. Proceedings.,[1st] International Conference on . IEEE, 1989, pp. 141–150

1989

Earlier work this paper cites.

D. E. Van Den Bout and T. K. Miller III, “A digital architecture employing stochasticism for the simulation of hopfield neural nets,” Circuits and Systems, IEEE Transactions on , vol. 36, no. 5, pp. 732–738, 1989

1989

Earlier work this paper cites.

M. Weinfeld, “A fully digital integrated cmos hopfield network including the learning algorithm,” in VLSI for Artificial Intelligence . Springer, 1989, pp. 169–178

1989

Earlier work this paper cites.

J. Tomberg, T. Ritoniemi, K. Kaski, and H. Tenhunen, “Fully digital neural network implementation based on pulse density modulation,” in Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989 . IEEE, 1989, pp. 12–7

1989

Earlier work this paper cites.

J. E. Hansen, J. Skelton, and D. Allstot, “A time-multiplexed switched-capacitor circuit for neural network applications,” in Circuits and Systems, 1989., IEEE International Symposium on . IEEE, 1989, pp. 2177–2180

1989

Earlier work this paper cites.

A. G. Andreou and K. A. Boahen, “Synthetic neural circuits using current-domain signal representations,” Neural Computation , vol. 1, no. 4, pp. 489–501, 1989

1989

Earlier work this paper cites.

K. A. Boahen, A. G. Andreou, P. O. Pouliquen, and A. Pavasovic, “Architectures for associative memories using current-mode analog mos circuits,” in Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI . MIT Press, 1989, pp. 175–193

1989

Earlier work this paper cites.

K. A. Boahen, P. O. Pouliquen, A. G. Andreou, and R. E. Jenkins, “A heteroassociative memory using current-mode mos analog vlsi circuits,” Circuits and Systems, IEEE Transactions on , vol. 36, no. 5, pp. 747–755, 1989

1989

Earlier work this paper cites.

J. R. Mann and S. Gilbert, “An analog self-organizing neural network chip,” in Advances in neural information processing systems , 1989, pp. 739–747

1989

Earlier work this paper cites.

Z. Butler, A. Murray, and A. Smith, “Vlsi bit-serial neural networks,” in VLSI for Artificial Intelligence . Springer, 1989, pp. 201–208

1989

Earlier work this paper cites.

Y. Hirai, K. Kamada, M. Yamada, and M. Ooyama, “A digital neuro-chip with unlimited connectability for large scale neural networks,” in Neural Networks, 1989. IJCNN., International Joint Conference on . IEEE, 1989, pp. 163–169

1989

Earlier work this paper cites.

M. Yasunaga, N. Masuda, M. Asai, M. Yamada, A. Masaki, and Y. Hirai, “A wafer scale integration neural network utilizing completely digital circuits,” in Neural Networks, 1989. IJCNN., International Joint Conference on . IEEE, 1989, pp. 213–217

1989

Earlier work this paper cites.

M. A. C. Maher, S. P. Deweerth, M. A. Mahowald, and C. A. Mead, “Implementing neural architectures using analog vlsi circuits,” Circuits and Systems, IEEE Transactions on , vol. 36, no. 5, pp. 643–652, 1989

1989

Earlier work this paper cites.

O. Rossetto, C. Jutten, J. Herault, and I. Kreuzer, “Analog vlsi synaptic matrices as building blocks for neural networks,” Micro, IEEE , vol. 9, no. 6, pp. 56–63, 1989

1989

Earlier work this paper cites.

S. Ryckebusch, J. M. Bower, and C. Mead, “Modeling small oscillating biological networks in analog vlsi,” 1989

1989

Earlier work this paper cites.

M. Holler, S. Tam, H. Castro, and R. Benson, “An electrically trainable artificial neural network (etann) with 10240 ’floating gate’ synapses,” in Neural Networks, 1989. IJCNN., International Joint Conference on . IEEE, 1989, pp. 191–196

1989

Earlier work this paper cites.

P. Mueller, J. Van der Spiegel, D. Blackman, T. Chiu, T. Clare, J. Dao, C. Donham, T. Hsieh, and M. Loinaz, “A general purpose analog neural computer,” in Neural Networks, 1989. IJCNN., International Joint Conference on . IEEE, 1989, pp. 177–182

1989

Earlier work this paper cites.

——, “A general purpose analog neural computer,” in Neural Networks, 1989. IJCNN., International Joint Conference on . IEEE, 1989, pp. 177–182

1989

Earlier work this paper cites.

P. Daniell, W. Waller, and D. Bisset, “An implementation of fully analogue sum-of-product neural models in vlsi,” in Artificial Neural Networks, 1989., First IEE International Conference on (Conf. Publ. No. 313) . IET, 1989, pp. 52–56

1989

Earlier work this paper cites.

A. Hamilton, A. F. Murray, and L. Tarassenko, “Programmable analog pulse-firing neural networks,” in Advances in neural information processing systems , 1989, pp. 671–677

1989

Earlier work this paper cites.

P. Houselander and J. Taylor, “Implementation of artificial neural networks using current mode analogue circuit techniques,” in Current Mode Analogue Circuits, IEE Colloquium on . IET, 1989, pp. 5–1

1989

Earlier work this paper cites.

A. Murray, A. Smith, and L. Tarassenko, “Fully-programmable analogue vlsi devices for the implementation of neural networks,” in VLSI for artificial intelligence . Springer, 1989, pp. 236–244

1989

Earlier work this paper cites.

F. Salam and Y. Wang, “Neural circuits for programmable analog mos vlsi implementation,” in Circuits and Systems, 1989., Proceedings of the 32nd Midwest Symposium on . IEEE, 1989, pp. 240–243

1989

Earlier work this paper cites.

D. B. Schwartz, R. E. Howard, and W. E. Hubbard, “A programmable analog neural network chip,” Solid-State Circuits, IEEE Journal of , vol. 24, no. 2, pp. 313–319, 1989

1989

Earlier work this paper cites.

J. Tomberg, T. Ritoniemi, H. Tenhunen, and K. Kaski, “Vlsi implementation of pulse density modulated neural network structure,” in Circuits and Systems, 1989., IEEE International Symposium on . IEEE, 1989, pp. 2104–2107

1989

Earlier work this paper cites.

J. I. Raffel, J. R. Mann, R. Berger, A. M. Soares, and S. L. Gilbert, “A generic architecture for wafer-scale neuromorphic systems,” Lincoln Laboratory Journal;(USA) , vol. 2, 1989

1989

Earlier work this paper cites.

D. R. Collins and P. A. Penz, “Considerations for neural network hardware implementations,” in Circuits and Systems, 1989., IEEE International Symposium on . IEEE, 1989, pp. 834–836

1989

Earlier work this paper cites.

E. A. Rietman, R. Frye, C. Wong, and C. Kornfeld, “Amorphous silicon photoconductive arrays for artificial neural networks,” Applied optics , vol. 28, no. 16, pp. 3474–3478, 1989

1989

Earlier work this paper cites.

Y. Suzuki and L. Atlas, “A study of regular architectures for digital implementation of neural networks,” in Circuits and Systems, 1989., IEEE International Symposium on . IEEE, 1989, pp. 82–85

1989

Earlier work this paper cites.

L. E. Atlas and Y. Suzuki, “Digital systems for artificial neural networks,” IEEE Circuits and Devices;(USA) , vol. 5, no. 6, 1989

1989

Earlier work this paper cites.

C. Mead, “Neuromorphic electronic systems,” Proceedings of the IEEE , vol. 78, no. 10, pp. 1629–1636, Oct 1990

1990

Earlier work this paper cites.

S. Bibyk, M. Ismail, T. Borgstrom, K. Adkins, R. Kaul, N. Khachab, and S. Dupuie, “Current-mode neural network building blocks for analog mos vlsi,” in Circuits and Systems, 1990., IEEE International Symposium on . IEEE, 1990, pp. 3283–3285

1990

Earlier work this paper cites.

F. Distante, M. Sami, and G. S. Gajani, “A general configurable architecture for wsi implementation for neural nets,” in Wafer Scale Integration, 1990. Proceedings.,[2nd] International Conference on . IEEE, 1990, pp. 116–123

1990

Earlier work this paper cites.

P. Hasler and L. Akers, “Vlsi neural systems and circuits,” in Computers and Communications, 1990. Conference Proceedings., Ninth Annual International Phoenix Conference on . IEEE, 1990, pp. 31–37

1990

Earlier work this paper cites.

J.-C. Lee and B. J. Sheu, “Parallel digital image restoration using adaptive vlsi neural chips,” in Computer Design: VLSI in Computers and Processors, 1990. ICCD’90. Proceedings, 1990 IEEE International Conference on . IEEE, 1990, pp. 126–129

1990

Earlier work this paper cites.

U. Çilingiroğlu, “Capacitive synapses for microelectronic neural networks,” in Circuits and Systems, 1990., IEEE International Symposium on . IEEE, 1990, pp. 2982–2985

1990

Earlier work this paper cites.

T. Borgstrom, M. Ismail, and S. Bibyk, “Programmable current-mode neural network for implementation in analogue mos vlsi,” IEE Proceedings G (Circuits, Devices and Systems) , vol. 137, no. 2, pp. 175–184, 1990

1990

Earlier work this paper cites.

W. Fisher, R. Fujimoto, and M. Okamura, “The lockheed programmable analog neural network processor,” in Neural Networks, 1990., 1990 IJCNN International Joint Conference on . IEEE, 1990, pp. 563–568

1990

Earlier work this paper cites.

F. M. Salam and M.-R. Choi, “An all-mos analog feedforward neural circuit with learning,” in Circuits and Systems, 1990., IEEE International Symposium on . IEEE, 1990, pp. 2508–2511

1990

Earlier work this paper cites.

S. M. Tam, B. Gupta, H. A. Castro, and M. Holler, “Learning on an analog vlsi neural network chip,” in Systems, Man and Cybernetics, 1990. Conference Proceedings., IEEE International Conference on . IEEE, 1990, pp. 701–703

1990

Earlier work this paper cites.

D. J. Weller and R. R. Spencer, “A process invariant analog neural network ic with dynamically refreshed weights,” in Circuits and Systems, 1990., Proceedings of the 33rd Midwest Symposium on . IEEE, 1990, pp. 273–276

1990

Earlier work this paper cites.

F. Distante, M. Sami, R. Stefanelli, and G. S. Gajani, “A configurable array architecture for wsi implementation of neural nets,” in Computers and Communications, 1990. Conference Proceedings., Ninth Annual International Phoenix Conference on . IEEE, 1990, pp. 44–51

1990

Earlier work this paper cites.

——, “Area compaction in silicon structures for neural net implementation,” Microprocessing and microprogramming , vol. 28, no. 1, pp. 139–143, 1990

1990

Earlier work this paper cites.

D. Hammerstrom, “A vlsi architecture for high-performance, low-cost, on-chip learning,” in Neural Networks, 1990., 1990 IJCNN International Joint Conference on . IEEE, 1990, pp. 537–544

1990

Earlier work this paper cites.

M. S. Tomlinson Jr and D. J. Walker, “Dnna: A digital neural network architecture,” in International Neural Network Conference . Springer, 1990, pp. 589–592

1990

Earlier work this paper cites.

M. S. Tomlinson Jr, D. J. Walker, and M. A. Sivilotti, “A digital neural network architecture for vlsi,” in Neural Networks, 1990., 1990 IJCNN International Joint Conference on . IEEE, 1990, pp. 545–550

1990

Earlier work this paper cites.

J. Theeten, M. Duranton, N. Mauduit, and J. Sirat, “The lneuro-chip: a digital vlsi with on-chip learning mechanism,” in International Neural Network Conference . Springer, 1990, pp. 593–596

1990

Earlier work this paper cites.

R. Inigo, A. Bonde, and B. Holcombe, “Self adjusting weights for hardware neural networks,” Electronics Letters , vol. 26, pp. 1630–1632, 1990

1990

Earlier work this paper cites.

O. Barkan, W. Smith, and G. Persky, “Design of coupling resistor networks for neural network hardware,” Circuits and Systems, IEEE Transactions on , vol. 37, no. 6, pp. 756–765, 1990

1990

Earlier work this paper cites.

K. Current and J. Current, “Cmos current-mode circuits for neural networks,” in Circuits and Systems, 1990., IEEE International Symposium on . IEEE, 1990, pp. 2971–2974

1990

Earlier work this paper cites.

H. P. Graf, R. Janow, D. Henderson, and R. Lee, “Reconfigurable neural net chip with 32k connections.” in NIPS , 1990, pp. 1032–1038

1990

Earlier work this paper cites.

L. Jackel, B. Boser, H. Graf, J. Denker, Y. Le Cun, D. Henderson, O. Matan, R. Howard, and H. Baird, “Vlsi implementations of electronic neural networks: An example in character recognition,” in Systems, Man and Cybernetics, 1990. Conference Proceedings., IEEE International Conference on . IEEE, 1990, pp. 320–322

1990

Earlier work this paper cites.

L. Jackel, B. Boser, J. Denker, H. Graf, Y. Le Cun, I. Guyon, D. Henderson, R. Howard, W. Hubbard, and S. Solla, “Hardware requirements for neural-net optical character recognition,” in Neural Networks, 1990., 1990 IJCNN International Joint Conference on . IEEE, 1990, pp. 855–861

1990

Earlier work this paper cites.

D. Van den Bout, P. Franzon, J. Paulos, T. Miller, W. Snyder, T. Nagle, and W. Liu, “Scalable vlsi implementations for neural networks,” Journal of VLSI signal processing systems for signal, image and video technology , vol. 1, no. 4, pp. 367–385, 1990

1990

Earlier work this paper cites.

B. W. Lee, J.-C. Lee, and B. J. Sheu, “Vlsi image processor using analog programmable synapses and neurons,” in Neural Networks, 1990., 1990 IJCNN International Joint Conference on . IEEE, 1990, pp. 575–580

1990

Earlier work this paper cites.

A. Masaki, Y. Hirai, and M. Yamada, “Neural networks in cmos: a case study,” Circuits and Devices Magazine, IEEE , vol. 6, no. 4, pp. 12–17, 1990

1990

Earlier work this paper cites.

W. Wike, D. Van den Bout, and T. Miller III, “The vlsi implementation of stonn,” in Neural Networks, 1990., 1990 IJCNN International Joint Conference on . IEEE, 1990, pp. 593–598

1990

Earlier work this paper cites.

J. E. Tomberg and K. K. Kaski, “Pulse-density modulation technique in vlsi implementations of neural network algorithms,” Solid-State Circuits, IEEE Journal of , vol. 25, no. 5, pp. 1277–1286, 1990

1990

Earlier work this paper cites.

P. W. Hollis and J. J. Paulos, “Artificial neural networks using mos analog multipliers,” Solid-State Circuits, IEEE Journal of , vol. 25, no. 3, pp. 849–855, 1990

1990

Earlier work this paper cites.

B. Maundy and E. El-Masry, “Pulse arithmetic in switched capacitor neural networks,” in Circuits and Systems, 1990., Proceedings of the 33rd Midwest Symposium on . IEEE, 1990, pp. 285–288

1990

Earlier work this paper cites.

A. Moopenn, T. Duong, and A. Thakoor, “Digital-analog hybrid synapse chips for electronic neural networks,” in Advances in Neural Information Processing Systems , 1990, pp. 769–776

1990

Earlier work this paper cites.

A. G. Andreou, K. A. Boahen, P. O. Pouliquen, A. Pavasovic, R. E. Jenkins, and K. Strohbehn, “Current-mode subthreshold mos circuits for analog vlsi neural systems,” IEEE transactions on neural networks/a publication of the IEEE Neural Networks Council , vol. 2, no. 2, pp. 205–213, 1990

1990

Earlier work this paper cites.

W.-C. Fang, B. J. Sheu, and J.-C. Lee, “Real-time computing of optical flow using adaptive vlsi neuroprocessors,” in Computer Design: VLSI in Computers and Processors, 1990. ICCD’90. Proceedings, 1990 IEEE International Conference on . IEEE, 1990, pp. 122–125

1990

Earlier work this paper cites.

L. Yang, L. Chua, and K. Krieg, “Vlsi implementation of cellular neural networks,” in Circuits and Systems, 1990., IEEE International Symposium on . IEEE, 1990, pp. 2425–2427

1990

Earlier work this paper cites.

J. Ouali and G. Saucier, “Fast generation of neuro-asics,” in International Neural Network Conference . Springer, 1990, pp. 563–567

1990

Earlier work this paper cites.

M. Yasunaga, N. Masuda, M. Yagyu, M. Asai, M. Yamada, and A. Masaki, “Design, fabrication and evaluation of a 5-inch wafer scale neural network lsi composed on 576 digital neurons,” in Neural Networks, 1990., 1990 IJCNN International Joint Conference on . IEEE, 1990, pp. 527–535

1990

Earlier work this paper cites.

A. G. Andreou, “Synthetic neural systems using current-mode circuits,” in Circuits and Systems, 1990., IEEE International Symposium on . IEEE, 1990, pp. 2428–2432

1990

Earlier work this paper cites.

E. A. Vittoz, “Analog vlsi implementation of neural networks,” in Circuits and Systems, 1990., IEEE International Symposium on . IEEE, 1990, pp. 2524–2527

1990

Earlier work this paper cites.

M. Brownlow, L. Tarassenko, and A. Murray, “Analogue computation using vlsi neural network devices,” Electronics Letters , vol. 26, no. 16, pp. 1297–1299, 1990

1990

Earlier work this paper cites.

F. Pelayo, A. Prieto, B. Pino, and P. Martin-Smith, “Analog vlsi implementation of a neural network with competitive learning,” in Cellular Neural Networks and their Applications, 1990. CNNA-90 Proceedings., 1990 IEEE International Workshop on . IEEE, 1990, pp. 197–205

1990

Earlier work this paper cites.

A. Rodriguez-Vazquez, R. Dominguez-Castro, A. Rueda, J. L. Huertas, and E. Sanchez-Sinencio, “Nonlinear switched capacitorneural’networks for optimization problems,” Circuits and Systems, IEEE Transactions on , vol. 37, no. 3, pp. 384–398, 1990

1990

Earlier work this paper cites.

H. Yanai and Y. Sawada, “Integrator neurons for analog neural networks,” Circuits and Systems, IEEE Transactions on , vol. 37, no. 6, pp. 854–856, 1990

1990

Earlier work this paper cites.

D. D. Corso and L. Reyneri, “Mixing analog and digital techniques for silicon neural networks,” in Circuits and Systems, 1990., IEEE International Symposium on . IEEE, 1990, pp. 2446–2449

1990

Earlier work this paper cites.

D. Del Corso and L. Reyneri, “Mixing analog and digital techniques for silicon neural networks,” in Circuits and Systems, 1990., IEEE International Symposium on . IEEE, 1990, pp. 2446–2449

1990

Earlier work this paper cites.

D. Del Corso, F. Gregoretti, and L. Reyneri, “Use of pulse rate and width modulations in a mixed analog/digital cell for artificial neural systems,” in Neurocomputing . Springer, 1990, pp. 157–160

1990

Earlier work this paper cites.

B. W. Lee and B. Sheu, “A compact and general-purpose neural chip with electrically programmable synapses,” in Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990 . IEEE, 1990, pp. 26–6

1990

Earlier work this paper cites.

J. Beerhold, M. Jansen, and R. Eckmiller, “Pulse-processing neural net hardware with selectable topology and adaptive weights and delays,” in Neural Networks, 1990., 1990 IJCNN International Joint Conference on . IEEE, 1990, pp. 569–574

1990

Earlier work this paper cites.

G. Cauwenberghs, C. F. Neugebauer, A. J. Agranat, and A. Yariv, “Large scale optoelectronic integration of asynchronous analog neural networks,” in International Neural Network Conference . Springer, 1990, pp. 551–554

1990

Earlier work this paper cites.

S. Thakoor, A. Moopenn, T. Daud, and A. Thakoor, “Solid-state thin-film memistor for electronic neural networks,” Journal of Applied Physics , vol. 67, no. 6, pp. 3132–3135, 1990

1990

Earlier work this paper cites.

D. J. Chen and B. J. Sheu, “Automatic layout generation for mixed analog-digital vlsi neural chips,” in Computer Design: VLSI in Computers and Processors, 1990. ICCD’90. Proceedings, 1990 IEEE International Conference on . IEEE, 1990, pp. 29–32

1990

Earlier work this paper cites.

A. J. Agranat, C. F. Neugebauer, and A. Yariv, “A ccd based neural network integrated circuit with 64k analog programmable synapses,” in Neural Networks, 1990., 1990 IJCNN International Joint Conference on . IEEE, 1990, pp. 551–555

1990

Earlier work this paper cites.

J. L. Meador, A. Wu, C. Cole, N. Nintunze, and P. Chintrakulchai, “Programmable impulse neural circuits.” IEEE transactions on neural networks/a publication of the IEEE Neural Networks Council , vol. 2, no. 1, pp. 101–109, 1990

1990

Earlier work this paper cites.

J. B. Burr, “Digital neural network implementations,” Neural networks, concepts, applications, and implementations , vol. 3, pp. 237–285, 1991

1991

Earlier work this paper cites.

M. Chiang, T. Lu, and J. Kuo, “Analogue adaptive neural network circuit,” IEE Proceedings G (Circuits, Devices and Systems) , vol. 138, no. 6, pp. 717–723, 1991

1991

Earlier work this paper cites.

K. Madani, P. Garda, E. Belhaire, and F. Devos, “Two analog counters for neural network implementation,” Solid-State Circuits, IEEE Journal of , vol. 26, no. 7, pp. 966–974, 1991

1991

Earlier work this paper cites.

A. F. Murray, D. Del Corso, and L. Tarassenko, “Pulse-stream vlsi neural networks mixing analog and digital techniques,” Neural Networks, IEEE Transactions on , vol. 2, no. 2, pp. 193–204, 1991

1991

Earlier work this paper cites.

L. Tarassenko, M. Brownlow, G. Marshall, J. Tombs, and A. Murray, “Real-time autonomous robot navigation using vlsi neural networks,” in Advances in neural information processing systems , 1991, pp. 422–428

1991

Earlier work this paper cites.

M. Mahowald and R. Douglas, “A silicon neuron,” 1991

1991

Earlier work this paper cites.

B. Linares-Barranco, E. Sánchez-Sinencio, A. Rodríguez-Vázquez, and J. L. Huertas, “A cmos implementation of fitzhugh-nagumo neuron model,” Solid-State Circuits, IEEE Journal of , vol. 26, no. 7, pp. 956–965, 1991

1991

Earlier work this paper cites.

B. Taheri et al. , “Proposed cmos vlsi implementation of an electronic neuron using multivalued signal processing,” in Multiple-Valued Logic, 1991., Proceedings of the Twenty-First International Symposium on . IEEE, 1991, pp. 203–209

1991

Earlier work this paper cites.

J. Meador, D. Watola, and N. Nintunze, “Vlsi implementation of a pulse hebbian learning law,” in Circuits and Systems, 1991., IEEE International Sympoisum on . IEEE, 1991, pp. 1287–1290

1991

Earlier work this paper cites.

H. Card, C. Schneider, and W. Moore, “Hebbian plasticity in mos synapses,” in IEE Proceedings F (Radar and Signal Processing) , vol. 138, no. 1. IET, 1991, pp. 13–16

1991

Earlier work this paper cites.

M.-R. Choi and F. M. Salam, “Implementation of feedforward artificial neural nets with learning using standard cmos vlsi technology,” in Circuits and Systems, 1991., IEEE International Sympoisum on . IEEE, 1991, pp. 1509–1512

1991

Earlier work this paper cites.

D. B. Feltham and W. Maly, “Physically realistic fault models for analog cmos neural networks,” Solid-State Circuits, IEEE Journal of , vol. 26, no. 9, pp. 1223–1229, 1991

1991

Earlier work this paper cites.

——, “A highly parallel digital architecture for neural network emulation,” in VLSI for artificial intelligence and neural networks . Springer, 1991, pp. 357–366

1991

Earlier work this paper cites.

D. Zhang, G. A. Jullien, W. C. Miller, and E. Swartzlander Jr, “Arithmetic for digital neural networks,” in Computer Arithmetic, 1991. Proceedings., 10th IEEE Symposium on . IEEE, 1991, pp. 58–63

1991

Earlier work this paper cites.

F. Distante, M. Sami, R. Stefanelli, and G. Storti-Gajani, “A compact and fast silicon implementation for layered neural nets,” in VLSI for Artificial Intelligence and Neural Networks . Springer, 1991, pp. 345–355

1991

Earlier work this paper cites.

D. Orrey, D. Myers, and J. Vincent, “A high performance digital processor for implementing large artificial neural networks,” in Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991 . IEEE, 1991, pp. 16–3

1991

Earlier work this paper cites.

J. Vincent and D. Myers, “Parameter selection for digital realisations of neural networks,” in Neural Networks: Design Techniques and Tools, IEE Colloquium on . IET, 1991, pp. 7–1

1991

Earlier work this paper cites.

C. Alippi and M. E. Nigri, “Hardware requirements to digital vlsi implementation of neural networks,” in Neural Networks, 1991. 1991 IEEE International Joint Conference on . IEEE, 1991, pp. 1873–1878

1991

Earlier work this paper cites.

H. Eguchi, T. Furuta, H. Horiguchi, S. Oteki, and T. Kitaguchi, “Neural network lsi chip with on-chip learning,” in Neural Networks, 1991., IJCNN-91-Seattle International Joint Conference on , vol. 1. IEEE, 1991, pp. 453–456

1991

Earlier work this paper cites.

B. E. Boser, E. Sackinger, J. Bromley, Y. Le Cun, and L. D. Jackel, “An analog neural network processor with programmable topology,” Solid-State Circuits, IEEE Journal of , vol. 26, no. 12, pp. 2017–2025, 1991

1991

Earlier work this paper cites.

B. Maundy and E. El-Masry, “Switched-capacitor realisations of artificial neural network learning schemes,” Electronics Letters , vol. 27, no. 1, pp. 85–87, 1991

1991

Earlier work this paper cites.

E. Sackinger, B. E. Boser, J. Bromley, Y. LeCun, and L. D. Jackel, “Application of the anna neural network chip to high-speed character recognition.” IEEE transactions on neural networks/a publication of the IEEE Neural Networks Council , vol. 3, no. 3, pp. 498–505, 1991

1991

Earlier work this paper cites.

M. Brownlow, L. Tarassenko, and A. Murray, “Results from pulse-stream vlsi neural network devices,” in VLSI for Artificial Intelligence and Neural Networks . Springer, 1991, pp. 215–224

1991

Earlier work this paper cites.

W. A. Fisher, R. J. Fujimoto, and R. C. Smithson, “A programmable analog neural network processor,” Neural Networks, IEEE Transactions on , vol. 2, no. 2, pp. 222–229, 1991

1991

Earlier work this paper cites.

P. Hasler and L. Akers, “Implementation of analog neural networks,” in Computers and Communications, 1991. Conference Proceedings., Tenth Annual International Phoenix Conference on . IEEE, 1991, pp. 32–38

1991

Earlier work this paper cites.

F. Salam and Y. Wang, “A learning algorithm for feedback neural network chips,” in Circuits and Systems, 1991., IEEE International Sympoisum on . IEEE, 1991, pp. 1377–1379

1991

Earlier work this paper cites.

A. THAKOOR, S. EBERHARDT, and T. Daud, “Electronic neural network for dynamic resource allocation,” in AIAA Computing in Aerospace… Conference: A Collection of Technical Papers , vol. 8. American Institute of Aeronautics and Astronautics, 1991, p. 339

1991

Earlier work this paper cites.

P. Alla, G. Dreyfus, J. Gascuel, A. Johannet, L. Personnaz, J. Roman, and M. Weinfeld, Silicon integration of learning algorithms and other auto-adaptive properties in a digital feedback neural network . Springer, 1991

1991

Earlier work this paper cites.

R. Aibara, Y. Mitsui, and T. Ae, “A cmos chip design of binary neural network with delayed synapses,” in Circuits and Systems, 1991., IEEE International Sympoisum on . IEEE, 1991, pp. 1307–1310

1991

Earlier work this paper cites.

B. W. Lee and B. J. Sheu, “Hardware annealing in electronic neural networks,” Circuits and Systems, IEEE Transactions on , vol. 38, no. 1, pp. 134–137, 1991

1991

Earlier work this paper cites.

B. J. Maundy and E. I. El-Masry, “Feedforward associative memory switched-capacitor artificial neural networks,” Analog Integrated Circuits and Signal Processing , vol. 1, no. 4, pp. 321–338, 1991

1991

Earlier work this paper cites.

U. Ruckert, “An associative memory with neural architecture and its vlsi implementation,” in System Sciences, 1991. Proceedings of the Twenty-Fourth Annual Hawaii International Conference on , vol. 1. IEEE, 1991, pp. 212–218

1991

Earlier work this paper cites.

C. Schneider and H. Card, “Analog vlsi models of mean field networks,” in VLSI for Artificial Intelligence and Neural Networks . Springer, 1991, pp. 185–194

1991

Earlier work this paper cites.

Y. Arima, K. Mashiko, K. Okada, T. Yamada, A. Maeda, H. Kondoh, and S. Kayano, “A self-learning neural network chip with 125 neurons and 10 k self-organization synapses,” Solid-State Circuits, IEEE Journal of , vol. 26, no. 4, pp. 607–611, 1991

1991

Earlier work this paper cites.

Y. Arima, K. Mashiko, K. Okada, T. Yamada, A. Maeda, H. Notani, H. Kondoh, and S. Kayano, “A 336-neuron, 28 k-synapse, self-learning neural network chip with branch-neuron-unit architecture,” Solid-State Circuits, IEEE Journal of , vol. 26, no. 11, pp. 1637–1644, 1991

1991

Earlier work this paper cites.

G. Cauwenberghs, C. F. Neugebauer, and A. Yariv, “An adaptive cmos matrix-vector multiplier for large scale analog hardware neural network applications,” in Neural Networks, 1991., IJCNN-91-Seattle International Joint Conference on , vol. 1. IEEE, 1991, pp. 507–511

1991

Earlier work this paper cites.

C. Schneider and H. Card, “Cmos implementation of analog hebbian synaptic learning circuits,” in Neural Networks, 1991., IJCNN-91-Seattle International Joint Conference on , vol. 1. IEEE, 1991, pp. 437–442

1991

Earlier work this paper cites.

——, “Analog cmos synaptic learning circuits adapted from invertebrate biology,” Circuits and Systems, IEEE Transactions on , vol. 38, no. 12, pp. 1430–1438, 1991

1991

Earlier work this paper cites.

——, “Analogue cmos hebbian synapses,” Electronics letters , vol. 27, no. 9, pp. 785–786, 1991

1991

Earlier work this paper cites.

B. J. Maundy and E. El-Masry, “A self-organizing switched-capacitor neural network,” Circuits and Systems, IEEE Transactions on , vol. 38, no. 12, pp. 1556–1563, 1991

1991

Earlier work this paper cites.

C. Lehmann and F. Blayo, “A vlsi implementation of a generic systolic synaptic building block for neural networks,” in VLSI for Artificial Intelligence and Neural Networks . Springer, 1991, pp. 325–334

1991

Earlier work this paper cites.

J. Cruz and L. Chua, “A cnn chip for connected component detection,” IEEE transactions on Circuits and Systems , vol. 38, no. 7, pp. 812–817, 1991

1991

Earlier work this paper cites.

K. Halonen, V. Porra, T. Roska, and L. Chua, “Programmable analog vlsi cnn chip with local digital logic,” in Circuits and Systems, 1991., IEEE International Sympoisum on . IEEE, 1991, pp. 1291–1294

1991

Earlier work this paper cites.

J. Tomberg and K. Kaski, “An effective training method for fully digital pulse-density modulated neural network architecture,” in Circuits and Systems, 1991., IEEE International Sympoisum on . IEEE, 1991, pp. 1497–1500

1991

Earlier work this paper cites.

U. Ramacher, “Synapse-x: a general-purpose neurocomputer architecture,” in Neural Networks, 1991. 1991 IEEE International Joint Conference on . IEEE, 1991, pp. 2168–2176

1991

Earlier work this paper cites.

U. Ramacher, J. Beichter, and N. Bruls, “Architecture of a general-purpose neural signal processor,” in Neural Networks, 1991., IJCNN-91-Seattle International Joint Conference on , vol. 1. IEEE, 1991, pp. 443–446

1991

Earlier work this paper cites.

M. Yasunaga, N. Masuda, M. Yagyu, M. Asai, K. Shibata, M. Ooyama, M. Yamada, T. Sakaguchi, and M. Hashimoto, “A self-learning neural network composed of 1152 digital neurons in wafer-scale lsis,” in Neural Networks, 1991. 1991 IEEE International Joint Conference on . IEEE, 1991, pp. 1844–1849

1991

Earlier work this paper cites.

P. Richert, L. Spaanenburg, M. Kespert, J. Nijhuis, M. Schwarz, and A. Siggelkow, “Asics for prototyping of pulse-density modulated neural networks,” in VLSI design of neural networks . Springer, 1991, pp. 125–151

1991

Earlier work this paper cites.

J. Vlontzos and S. Kung, “Digital neural network architecture and implementation,” in VLSI Design of Neural Networks . Springer, 1991, pp. 205–227

1991

Earlier work this paper cites.

Y. Wang and F. Salam, “Experiments using cmos neural network chips as pattern/character recognizers,” in Circuits and Systems, 1991., IEEE International Sympoisum on . IEEE, 1991, pp. 1196–1199

1991

Earlier work this paper cites.

J.-D. Gascuel, M. Weinfeld, and S. Chakroun, “A digital cmos fully connected neural network with in-circuit learning capability and automatic identification of spurious attractors.” in Neural Networks, 1991., IJCNN-91-Seattle International Joint Conference on , vol. 2. IEEE, 1991, p. 923

1991

Earlier work this paper cites.

M. Griffin, G. Tahara, K. Knorpp, R. Pinkham, and B. Riley, “An 11-million transistor neural network execution engine,” in Solid-State Circuits Conference, 1991. Digest of Technical Papers. 38th ISSCC., 1991 IEEE International . IEEE, 1991, pp. 180–313

1991

Earlier work this paper cites.

S. Lucas and B. Damper, “Syntactic neural networks in vlsi,” in VLSI for Artificial Intelligence and Neural Networks . Springer, 1991, pp. 305–314

1991

Earlier work this paper cites.

J. Ouali, G. Saucier, and J. Trilhe, “Fast design of digital dedicated neuro chips,” in VLSI Design of Neural Networks . Springer, 1991, pp. 187–203

1991

Earlier work this paper cites.

G. Moon, M. E. Zaghloul, and R. W. Newcomb, “Vlsi implementation of synaptic weighting and summing in pulse coded neural-type cells.” IEEE transactions on neural networks/a publication of the IEEE Neural Networks Council , vol. 3, no. 3, pp. 394–403, 1991

1991

Earlier work this paper cites.

W. Waller, D. Bisset, and P. Daniell, “An analogue neuron suitable for a data frame architecture,” in VLSI for Artificial Intelligence and Neural Networks . Springer, 1991, pp. 195–204

1991

Earlier work this paper cites.

C. Neugebauer and A. Yariv, “A parallel analog ccd/cmos neural network ic,” in Neural Networks, 1991., IJCNN-91-Seattle International Joint Conference on , vol. 1. IEEE, 1991, pp. 447–451

1991

Earlier work this paper cites.

B. W. Lee, B. J. Sheu, and H. Yang, “Analog floating-gate synapses for general-purpose vlsi neural computation,” IEEE transactions on circuits and systems , vol. 38, no. 6, pp. 654–658, 1991

1991

Earlier work this paper cites.

R. C. Frye, E. A. Rietman, and C. C. Wong, “Back-propagation learning and nonidealities in analog neural network hardware,” Neural Networks, IEEE Transactions on , vol. 2, no. 1, pp. 110–117, 1991

1991

Earlier work this paper cites.

D. Livingston, S. Albin, and S. Park, “A new method for storing weights in analog neural hardware,” in Southeastcon’91., IEEE Proceedings of . IEEE, 1991, pp. 86–88

1991

Earlier work this paper cites.

M. Nigri, P. Treleaven, and M. Vellasco, “Silicon compilation of neural networks,” in CompEuro’91. Advanced Computer Technology, Reliable Systems and Applications. 5th Annual European Computer Conference. Proceedings. IEEE, 1991, pp. 541–546

1991

Earlier work this paper cites.

L. M. Reyneri and E. Filippi, “An analysis on the performance of silicon implementations of backpropagation algorithms for artificial neural networks,” Computers, IEEE Transactions on , vol. 40, no. 12, pp. 1380–1389, 1991

1991

Earlier work this paper cites.

C. Alippi and G. Storti-Gajani, “Simple approximation of sigmoidal functions: realistic design of digital neural networks capable of learning,” in Circuits and Systems, 1991., IEEE International Sympoisum on . IEEE, 1991, pp. 1505–1508

1991

Earlier work this paper cites.

P. H. Leong and M. A. Jabri, “A vlsi neural network for morphology classification,” in Neural Networks, 1992. IJCNN., International Joint Conference on , vol. 2. IEEE, 1992, pp. 678–683

1992

Earlier work this paper cites.

J. G. Elias, H.-H. Chu, and S. M. Meshreki, “Silicon implementation of an artificial dendritic tree,” in Neural Networks, 1992. IJCNN., International Joint Conference on , vol. 1. IEEE, 1992, pp. 154–159

1992

Earlier work this paper cites.

J. G. Elias, H.-H. Chu, and S. Meshreki, “A neuromorphic impulsive circuit for processing dynamic signals,” in Circuits and Systems, 1992. ISCAS’92. Proceedings., 1992 IEEE International Symposium on , vol. 5. IEEE, 1992, pp. 2208–2211

1992

Earlier work this paper cites.

P. Murtagh and A. Tsoi, “Implementation issues of sigmoid function and its derivative for vlsi digital neural networks,” IEE Proceedings E (Computers and Digital Techniques) , vol. 139, no. 3, pp. 207–214, 1992

1992

Earlier work this paper cites.

M. Abo-Elsoud, “Analog circuits for electronic neural network,” in Circuits and Systems, 1992., Proceedings of the 35th Midwest Symposium on . IEEE, 1992, pp. 5–8

1992

Earlier work this paper cites.

S. Kim, Y.-C. Shin, N. C. Bogineni, and R. Sridhar, “A programmable analog cmos synapse for neural networks,” Analog Integrated Circuits and Signal Processing , vol. 2, no. 4, pp. 345–352, 1992

1992

Earlier work this paper cites.

J. Lazzaro, “Low-power silicon spiking neurons and axons,” in Circuits and Systems, 1992. ISCAS’92. Proceedings., 1992 IEEE International Symposium on , vol. 5. IEEE, 1992, pp. 2220–2223

1992

Earlier work this paper cites.

Y. Arima, M. Murasaki, T. Yamada, A. Maeda, and H. Shinohara, “A refreshable analog vlsi neural network chip with 400 neurons and 40 k synapses,” in Solid-State Circuits Conference, 1992. Digest of Technical Papers. 39th ISSCC, 1992 IEEE International . IEEE, 1992, pp. 132–133

1992

Earlier work this paper cites.

T.-H. Botha, “An analog cmos programmable and configurable neural network,” in Pattern Recognition, 1992. Vol. IV. Conference D: Architectures for Vision and Pattern Recognition, Proceedings., 11th IAPR International Conference on . IEEE, 1992, pp. 222–224

1992

Earlier work this paper cites.

J. Choi and B. J. Sheu, “Vlsi design of compact and high-precision analog neural network processors,” in Neural Networks, 1992. IJCNN., International Joint Conference on , vol. 2. IEEE, 1992, pp. 637–641

1992

Earlier work this paper cites.

T. Duong, S. Eberhardt, M. Tran, T. Daud, and A. Thakoor, “Learning and optimization with cascaded vlsi neural network building-block chips,” in Neural Networks, 1992. IJCNN., International Joint Conference on , vol. 1. IEEE, 1992, pp. 184–189

1992

Earlier work this paper cites.

S. P. Eberhardt, R. Tawel, T. X. Brown, T. Daud, and A. Thakoor, “Analog vlsi neural networks: Implementation issues and examples in optimization and supervised learning,” Industrial Electronics, IEEE Transactions on , vol. 39, no. 6, pp. 552–564, 1992

1992

Earlier work this paper cites.

M. Jabri and B. Flower, “Weight perturbation: An optimal architecture and learning technique for analog vlsi feedforward and recurrent multilayer networks,” Neural Networks, IEEE Transactions on , vol. 3, no. 1, pp. 154–157, 1992

1992

Earlier work this paper cites.

J. Lansner, T. Lehmann et al. , “A neuron-and a synapse chip for artificial neural networks,” in Solid-State Circuits Conference, 1992. ESSCIRC’92. Eighteenth European . IEEE, 1992, pp. 213–216

1992

Earlier work this paper cites.

J. B. Lont and W. Guggenbÿhl, “Analog cmos implementation of a multilayer perceptron with nonlinear synapses,” Neural Networks, IEEE Transactions on , vol. 3, no. 3, pp. 457–465, 1992

1992

Earlier work this paper cites.

A. F. Murray, “Analog vlsi and multi-layer perceptions-accuracy, noise and on-chip learning,” Neurocomputing , vol. 4, no. 6, pp. 301–310, 1992

1992

Earlier work this paper cites.

A. Nosratinia, M. Ahmadi, and M. Shridhar, “Implementation issues in a multi-stage feed-forward analog neural network,” in Neural Networks, 1992. IJCNN., International Joint Conference on , vol. 2. IEEE, 1992, pp. 642–647

1992

Earlier work this paper cites.

S. Tam, M. Holler, J. Brauch, A. Pine, A. Peterson, S. Anderson, and S. Deiss, “A reconfigurable multi-chip analog neural network: recognition and back-propagation training,” in Neural Networks, 1992. IJCNN., International Joint Conference on , vol. 2. IEEE, 1992, pp. 625–630

1992

Earlier work this paper cites.

J. Van der Spiegel, P. Mueller, D. Blackman, P. Chance, C. Donham, R. Etienne-Cummings, and P. Kinget, “An analog neural computer with modular architecture for real-time dynamic computations,” Solid-State Circuits, IEEE Journal of , vol. 27, no. 1, pp. 82–92, 1992

1992

Earlier work this paper cites.

S. Wolpert, L. Lee, J. F. Heisler et al. , “Circuits for a vlsi-based standalone backpropagation neural network,” in Bioengineering Conference, 1992., Proceedings of the 1992 Eighteenth IEEE Annual Northeast . IEEE, 1992, pp. 47–48

1992

Earlier work this paper cites.

Y.-C. Kim and M. Shanblatt, “An implementable digital multilayer neural network (dmnn),” in Neural Networks, 1992. IJCNN., International Joint Conference on , vol. 2. IEEE, 1992, pp. 594–600

1992

Earlier work this paper cites.

E. Torbey and B. Haroun, “Architectural synthesis for digital neural networks,” in Neural Networks, 1992. IJCNN., International Joint Conference on , vol. 2. IEEE, 1992, pp. 601–606

1992

Earlier work this paper cites.

C.-F. Chang and B. Sheu, “Digital vlsi multiprocessor design for neurocomputers,” in Neural Networks, 1992. IJCNN., International Joint Conference on , vol. 2. IEEE, 1992, pp. 1–6

1992

Earlier work this paper cites.

J.-H. Chung, H. Yoon, and S. R. Maeng, “A systolic array exploiting the inherent parallelisms of artificial neural networks,” Microprocessing and Microprogramming , vol. 33, no. 3, pp. 145–159, 1992

1992

Earlier work this paper cites.

J. Wawrzynek, K. Asanovic, and N. Morgan, “The design of a neuro-microprocessor,” IEEE transactions on neural networks/a publication of the IEEE Neural Networks Council , vol. 4, no. 3, pp. 394–399, 1992

1992

Earlier work this paper cites.

D. D. Corso, F. Gregoretti, L. Reyneri, and A. Allasia, “A pattern recognition demonstrator based on a silicon neural chip,” in Solid-State Circuits Conference, 1992. ESSCIRC’92. Eighteenth European . IEEE, 1992, pp. 207–212

1992

Earlier work this paper cites.

A. Nosratinia, M. Ahmadi, M. Shridhar, and G. Jullien, “A hybrid architecture for feed-forward multi-layer neural networks,” in Circuits and Systems, 1992. ISCAS’92. Proceedings., 1992 IEEE International Symposium on , vol. 3. IEEE, 1992, pp. 1541–1544

1992

Earlier work this paper cites.

E. Säckinger, B. E. Boser, and L. D. Jackel, “A neurocomputer board based on the anna neural network chip,” in Advances in Neural Information Processing Systems , 1992, pp. 773–780

1992

Earlier work this paper cites.

S. Erdogan and A. Wahab, “Design of rm-nc: A reconfigurable neurocomputer for massively parallel-pipelined computations,” in Neural Networks, 1992. IJCNN., International Joint Conference on , vol. 2. IEEE, 1992, pp. 33–38

1992

Earlier work this paper cites.

B. Linares-Barranco, E. Sanchez-Sinencio, A. Rodriguez-Vazquez, and J. L. Huertas, “A modular t-mode design approach for analog neural network hardware implementations,” Solid-State Circuits, IEEE Journal of , vol. 27, no. 5, pp. 701–713, 1992

1992

Earlier work this paper cites.

B. Linares-Barranco, E. Sanchez-Sinencio, A. Rodriguez-Vazquez, and J. Huertas, “Modular analog continuous-time vlsi neural networks with on-chip hebbian learning and analog storage,” in Circuits and Systems, 1992. ISCAS’92. Proceedings., 1992 IEEE International Symposium on , vol. 3. IEEE, 1992, pp. 1533–1536

1992

Earlier work this paper cites.

A. Johannet, L. Personnaz, G. Dreyfus, J.-D. Gascuel, and M. Weinfeld, “Specification and implementation of a digital hopfield-type associative memory with on-chip training,” Neural Networks, IEEE Transactions on , vol. 3, no. 4, pp. 529–539, 1992

1992

Earlier work this paper cites.

A. Jayakumar and J. Alspector, “A cascadable neural network chip set with on-chip learning using noise and gain annealing,” in Custom Integrated Circuits Conference, 1992., Proceedings of the IEEE 1992 . IEEE, 1992, pp. 19–5

1992

Earlier work this paper cites.

S. Sato, M. Yumine, T. Yama, J. Murota, K. Nakajima, and Y. Sawada, “Lsi implementation of pulse-output neural network with programmable synapse,” in Neural Networks, 1992. IJCNN., International Joint Conference on , vol. 1. IEEE, 1992, pp. 172–177

1992

Earlier work this paper cites.

T. Shima, T. Kimura, Y. Kamatani, T. Itakura, Y. Fujita, and T. Iida, “Neuro chips with on-chip backprop and/or hebbian learning,” in Solid-State Circuits Conference, 1992. Digest of Technical Papers. 39th ISSCC, 1992 IEEE International . IEEE, 1992, pp. 138–139

1992

Earlier work this paper cites.

B. Sheu, J. Choi, and C.-F. Chang, “An analog neural network processor for self-organizing mapping,” in Solid-State Circuits Conference, 1992. Digest of Technical Papers. 39th ISSCC, 1992 IEEE International . IEEE, 1992, pp. 136–137

1992

Earlier work this paper cites.

N. Mauduit, M. Duranton, J. Gobert, and J.-A. Sirat, “Lneuro 1.0: A piece of hardware lego for building neural network systems,” Neural Networks, IEEE Transactions on , vol. 3, no. 3, pp. 414–422, 1992

1992

Earlier work this paper cites.

W.-C. Fang, B. J. Sheu, O.-C. Chen, and J. Choi, “A vlsi neural processor for image data compression using self-organization networks,” Neural Networks, IEEE Transactions on , vol. 3, no. 3, pp. 506–518, 1992

1992

Earlier work this paper cites.

H. Harrer, J. A. Nossek, and R. Stelzl, “An analog implementation of discrete-time cellular neural networks,” Neural Networks, IEEE Transactions on , vol. 3, no. 3, pp. 466–476, 1992

1992

Earlier work this paper cites.

H. Ishii, T. Shibata, H. Kosaka, and T. Ohmi, “Hardware-backpropagation learning of neuron mos neural networks,” in Electron Devices Meeting, 1992. IEDM’92. Technical Digest., International . IEEE, 1992, pp. 435–438

1992

Earlier work this paper cites.

P. Hasler and L. Akers, “Circuit implementation of a trainable neural network using the generalized hebbian algorithm with supervised techniques,” in Neural Networks, 1992. IJCNN., International Joint Conference on , vol. 1. IEEE, 1992, pp. 160–165

1992

Earlier work this paper cites.

U. Ramacher, “Synapse?a neurocomputer that synthesizes neural algorithms on a parallel systolic engine,” Journal of Parallel and Distributed Computing , vol. 14, no. 3, pp. 306–318, 1992

1992

Earlier work this paper cites.

C. Y. Fu, B. Law, G. Chapline, and D. Swenson, “A novel technology for fabricating customizable vlsi artificial neural network chips,” in Neural Networks, 1992. IJCNN., International Joint Conference on , vol. 2. IEEE, 1992, pp. 631–636

1992

Earlier work this paper cites.

R. Mason, W. Robertson, and D. Pincock, “An hierarchical vlsi neural network architecture,” Solid-State Circuits, IEEE Journal of , vol. 27, no. 1, pp. 106–108, 1992

1992

Earlier work this paper cites.

K. Uchimura, O. Saito, and Y. Amemiya, “A high-speed digital neural network chip with low-power chain-reaction architecture,” Solid-State Circuits, IEEE Journal of , vol. 27, no. 12, pp. 1862–1867, 1992

1992

Earlier work this paper cites.

B. A. White and M. I. Elmasry, “The digi-neocognitron: a digital neocognitron neural network model for vlsi,” Neural Networks, IEEE Transactions on , vol. 3, no. 1, pp. 73–85, 1992

1992

Earlier work this paper cites.

A. Cichocki, J. Ramirez-Angulo, and R. Unbehauen, “Architectures for analog vlsi implementation of neural networks for solving linear equations with inequality constraints,” in Circuits and Systems, 1992. ISCAS’92. Proceedings., 1992 IEEE International Symposium on , vol. 3. IEEE, 1992, pp. 1529–1532

1992

Earlier work this paper cites.

P. Mueller, J. Van der Spiegel, V. Agami, D. Blackman, P. Chance, C. Donham, R. Etienne, J. Flinn, J. Kim, M. Massa et al. , “Design and performance of a prototype analog neural computer,” Neurocomputing , vol. 4, no. 6, pp. 311–324, 1992

1992

Earlier work this paper cites.

T. Shibata and T. Ohmi, “A self-learning neural-network lsi using neuron mosfets,” in VLSI Technology, 1992. Digest of Technical Papers. 1992 Symposium on . IEEE, 1992, pp. 84–85

1992

Earlier work this paper cites.

J. Tomberg and K. Kaski, “Feasibility of synchronous pulse-density modulation arithmetic in integrated circuit implementations of artificial neural networks,” in Circuits and Systems, 1992. ISCAS’92. Proceedings., 1992 IEEE International Symposium on , vol. 5. IEEE, 1992, pp. 2232–2235

1992

Earlier work this paper cites.

B. W. Lee and B. J. Sheu, “General-purpose neural chips with electrically programmable synapses and gain-adjustable neurons,” IEEE journal of solid-state circuits , vol. 27, no. 9, pp. 1299–1302, 1992

1992

Earlier work this paper cites.

S. Satyanarayana, Y. Tsividis, and H. P. Graf, “A reconfigurable vlsi neural network,” Solid-State Circuits, IEEE Journal of , vol. 27, no. 1, pp. 67–81, 1992

1992

Earlier work this paper cites.

M. DeYong, R. L. Findley, and C. Fields, “The design, fabrication, and test of a new vlsi hybrid analog-digital neural processing element,” Neural Networks, IEEE Transactions on , vol. 3, no. 3, pp. 363–374, 1992

1992

Earlier work this paper cites.

M. DeYong and C. Fields, “Applications of hybrid analog-digital neural networks in signal processing,” in Proc. IEEE Int. Symp. on Circuits and Systems , 1992, pp. 2212–2215

1992

Earlier work this paper cites.

M. L. Mumford, D. K. Andes, and L. R. Kern, “The mod 2 neurocomputer system design,” Neural Networks, IEEE Transactions on , vol. 3, no. 3, pp. 423–433, 1992

1992

Earlier work this paper cites.

D. Durfee, F. Shoucair et al. , “Comparison of floating gate neural network memory cells in standard vlsi cmos technology,” Neural Networks, IEEE Transactions on , vol. 3, no. 3, pp. 347–353, 1992

1992

Earlier work this paper cites.

C.-K. Sin, A. Kramer, V. Hu, R. R. Chu, and P. K. Ko, “Eeprom as an analog storage device, with particular applications in neutral networks,” Electron Devices, IEEE Transactions on , vol. 39, no. 6, pp. 1410–1419, 1992

1992

Earlier work this paper cites.

M. Adé, R. Lauwereins, and J. Peperstraete, “A fast simulator for neural networks on dsps or fpgas,” in Neural Networks for Signal Processing [1992] II., Proceedings of the 1992 IEEE-SP Workshop . IEEE, 1992, pp. 597–605

1992

Earlier work this paper cites.

M. Mahowald, Evolving analog VLSI neurons . Chap, 1992, vol. 15

1992

Earlier work this paper cites.

T. Fukuda, T. Shibata, M. Tokita, and T. Mitsuoka, “Neuromorphic control: adaptation and learning,” Industrial Electronics, IEEE Transactions on , vol. 39, no. 6, pp. 497–503, 1992

1992

Earlier work this paper cites.

R. C. Frye and E. A. Reitman, “Experimental studies of analog neural networks,” in Frontiers of Computing Systems Research . Springer, 1992, pp. 239–290

1992

Earlier work this paper cites.

P. W. Hollis and J. J. Paulos, “An analog bicmos hopfield neuron,” in Analog VLSI Neural Networks . Springer, 1993, pp. 11–17

1993

Earlier work this paper cites.

J. Alspector, R. Meir, B. Yuhas, A. Jayakumar, and D. Lippe, “A parallel gradient descent method for learning in analog vlsi neural networks,” in Advances in neural information processing systems , 1993, pp. 836–844

1993

Earlier work this paper cites.

Y. K. Choi and S.-Y. Lee, “Subthreshold mos implementation of neural networks with on-chip error backpropagation learning,” in Neural Networks, 1993. IJCNN’93-Nagoya. Proceedings of 1993 International Joint Conference on , vol. 1. IEEE, 1993, pp. 849–852

1993

Earlier work this paper cites.

J. Choi, S. H. Bang, and B. J. Sheu, “A programmable analog vlsi neural network processor for communication receivers,” Neural Networks, IEEE Transactions on , vol. 4, no. 3, pp. 484–495, 1993

1993

Earlier work this paper cites.

——, “A programmable vlsi neural network processor for digital communications,” in Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993 . IEEE, 1993, pp. 16–5

1993

Earlier work this paper cites.

B. K. Dolenko and H. C. Card, “The effects of analog hardware properties on backpropagation networks with on-chip learning,” in Neural Networks, 1993., IEEE International Conference on . IEEE, 1993, pp. 110–115

1993

Earlier work this paper cites.

B. Dolenko and H. Card, “Neural learning in analogue hardware: Effects of component variation from fabrication and from noise,” Electronics letters , vol. 29, no. 8, pp. 693–694, 1993

1993

Earlier work this paper cites.

J. Donald and L. A. Akers, “An adaptive neural processing node,” Neural Networks, IEEE Transactions on , vol. 4, no. 3, pp. 413–426, 1993

1993

Earlier work this paper cites.

K. Hirotsu and M. A. Brooke, “An analog neural network chip with random weight change learning algorithm,” in Neural Networks, 1993. IJCNN’93-Nagoya. Proceedings of 1993 International Joint Conference on , vol. 3. IEEE, 1993, pp. 3031–3034

1993

Earlier work this paper cites.

J. B. Lont, “High-density analog-eeprom based neural network,” in ICANN?93 . Springer, 1993, pp. 1062–1065

1993

Earlier work this paper cites.

Y. Maeda, H. Hirano, and Y. Kanata, “An analog neural network circuit with a learning rule via simultaneous perturbation,” in Neural Networks, 1993. IJCNN’93-Nagoya. Proceedings of 1993 International Joint Conference on , vol. 1. IEEE, 1993, pp. 853–856

1993

Earlier work this paper cites.

H.-J. Oh and F. M. Salam, “A modular analog chip for feed-forward networks with on-chip learning,” in Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on . IEEE, 1993, pp. 766–769

1993

Earlier work this paper cites.

L. Song, M. I. Elmasry, and A. Vannelli, “Analog neural network building blocks based on current mode subthreshold operation,” in Circuits and Systems, 1993., ISCAS’93, 1993 IEEE International Symposium on . IEEE, 1993, pp. 2462–2465

1993

Earlier work this paper cites.

R. Tawel, “Learning in analog neural network hardware,” Computers & electrical engineering , vol. 19, no. 6, pp. 453–467, 1993

1993

Earlier work this paper cites.

J. Tombs, L. Tarassenko, G. Cairns, and A. Murray, “Cascadability and in-situ learning for vlsi multi-layer networks,” in Artificial Neural Networks, 1993., Third International Conference on . IET, 1993, pp. 56–60

1993

Earlier work this paper cites.

Y. Wang, “Analog cmos implementation of backward error propagation,” in Neural Networks, 1993., IEEE International Conference on . IEEE, 1993, pp. 701–706

1993

Earlier work this paper cites.

Y.-C. Kim, M. Shanblatt et al. , “A vlsi-based digital multilayer neural network architecture,” in VLSI, 1993.’Design Automation of High Performance VLSI Systems’, Proceedings., Third Great Lakes Symposium on . IEEE, 1993, pp. 27–31

1993

Earlier work this paper cites.

S. Pakzad and P. Plaskonos, “Implementation of a digital modular chip for a reconfigurable artificial neural network,” in PARLE’93 Parallel Architectures and Languages Europe . Springer, 1993, pp. 700–703

1993

Earlier work this paper cites.

P. Plaskonos, S. Pakzad, B. Jin, and A. Hurson, “Design of a modular chip for a reconfigurable artificial neural network,” in Developing and Managing Intelligent System Projects, 1993., IEEE International Conference on . IEEE, 1993, pp. 55–62

1993

Earlier work this paper cites.

J. Tuazon, K. Hamidian, and L. Guyette, “A new digital neural network and its application,” in Electrical and Computer Engineering, 1993. Canadian Conference on . IEEE, 1993, pp. 481–485

1993

Earlier work this paper cites.

D. J. Myers, J. M. Vincent, and D. A. Orrey, “Hannibal: A vlsi building block for neural networks with on-chip backpropagation learning,” Neurocomputing , vol. 5, no. 1, pp. 25–37, 1993

1993

Earlier work this paper cites.

S. Oteki, A. Hashimoto, T. Furuta, S. Motomura, T. Watanabe, D. Stork, and H. Eguchi, “A digital neural network vlsi with on-chip learning using stochastic pulse encoding,” in Neural Networks, 1993. IJCNN’93-Nagoya. Proceedings of 1993 International Joint Conference on , vol. 3. IEEE, 1993, pp. 3039–3045

1993

Earlier work this paper cites.

Z. Tang, O. Ishizuka, and H. Matsumoto, “Backpropagation learning in analog t-model neural network hardware,” in Neural Networks, 1993. IJCNN’93-Nagoya. Proceedings of 1993 International Joint Conference on , vol. 1. IEEE, 1993, pp. 899–902

1993

Earlier work this paper cites.

J. Franca et al. , “A mixed-mode architecture for implementation of analog neural networks with digital programmability,” in Neural Networks, 1993. IJCNN’93-Nagoya. Proceedings of 1993 International Joint Conference on , vol. 1. IEEE, 1993, pp. 887–890

1993

Earlier work this paper cites.

A. Passos Almeida and J. Franca, “A mixed-mode architecture for implementation of analog neural networks with digital programmability,” in Neural Networks, 1993. IJCNN’93-Nagoya. Proceedings of 1993 International Joint Conference on , vol. 1. IEEE, 1993, pp. 887–890

1993

Earlier work this paper cites.

N. Yazdi, M. Ahmadi, G. A. Jullien, and M. Shridhar, “Pipelined analog multi-layer feedforward neural networks,” in Circuits and Systems, 1993., ISCAS’93, 1993 IEEE International Symposium on . IEEE, 1993, pp. 2768–2771

1993

Earlier work this paper cites.

N. M. Botros and M. Abdul-Aziz, “Hardware implementation of an artificial neural network,” in Neural Networks, 1993., IEEE International Conference on . IEEE, 1993, pp. 1252–1257

1993

Earlier work this paper cites.

J. A. Lansner and T. Lehmann, “An analog cmos chip set for neural networks with arbitrary topologies,” Neural Networks, IEEE Transactions on , vol. 4, no. 3, pp. 441–444, 1993

1993

Earlier work this paper cites.

P. Hylander, J. Meader, and E. Frie, “Vlsi implementation of pulse coded winner take all networks,” in Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on . IEEE, 1993, pp. 758–761

1993

Earlier work this paper cites.

C. Lehmann, M. Viredaz, and F. Blayo, “A generic systolic array building block for neural networks with on-chip learning,” Neural Networks, IEEE Transactions on , vol. 4, no. 3, pp. 400–407, 1993

1993

Earlier work this paper cites.

M. Yasunaga, N. Masuda, M. Yagyu, M. Asai, K. Shibata, M. Ooyama, M. Yamada, T. Sakaguchi, and M. Hashimoto, “A self-learning digital neural network using wafer-scale lsi,” Solid-State Circuits, IEEE Journal of , vol. 28, no. 2, pp. 106–114, 1993

1993

Earlier work this paper cites.

B. Linares-Barranco, E. Sánchez-Sinencio, A. Rodriguez-Vazquez, and J. L. Huertas, “A cmos analog adaptive bam with on-chip learning and weight refreshing,” Neural Networks, IEEE Transactions on , vol. 4, no. 3, pp. 445–455, 1993

1993

Earlier work this paper cites.

M. van Daalen, P. Jeavons, and J. Shawe-Taylor, “A stochastic neural architecture that exploits dynamically reconfigurable fpgas,” in FPGAs for Custom Computing Machines, 1993. Proceedings. IEEE Workshop on . IEEE, 1993, pp. 202–211

1993

Earlier work this paper cites.

C. R. Schneider and H. C. Card, “Analog cmos deterministic boltzmann circuits,” Solid-State Circuits, IEEE Journal of , vol. 28, no. 8, pp. 907–914, 1993

1993

Earlier work this paper cites.

G. Dalla Betta, S. Graffi, Z. M. Kovacs, and G. Masetti, “Cmos implementation of an analogically programmable cellular neural network,” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on , vol. 40, no. 3, pp. 206–215, 1993

1993

Earlier work this paper cites.

A. Rodriguez-Vazquez, S. Espejo, R. Dominguez-Castron, J. L. Huertas, and E. Sanchez-Sinencio, “Current-mode techniques for the implementation of continuous-and discrete-time cellular neural networks,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing , vol. 40, no. 3, pp. 132–146, 1993

1993

Earlier work this paper cites.

Y.-H. Kuo, C.-I. Kao, and J.-J. Chen, “A fuzzy neural network model and its hardware implementation,” Fuzzy Systems, IEEE Transactions on , vol. 1, no. 3, pp. 171–183, 1993

1993

Earlier work this paper cites.

J. Beichter, N. Bruels, E. Sicheneder, U. Ramacher, and H. Klar, “Design of a general-purpose neural signal processor,” Neurocomputing , vol. 5, no. 1, pp. 17–23, 1993

1993

Earlier work this paper cites.

H. Nakahira, S. Sakiyama, M. Maruyama, K. Hasegawa, T. Kouda, S. Maruno, Y. Shimeki, T. Satonaka, and Y. Nagano, “A digital neuroprocessor using quantizer neurons,” in VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on . IEEE, 1993, pp. 35–36

1993

Earlier work this paper cites.

T. Watanabe, K. Kimura, M. Aoki, T. Sakata, and K. Ito, “A single 1.5-v digital chip for a 10 6 synapse neural network,” Neural Networks, IEEE Transactions on , vol. 4, no. 3, pp. 387–393, 1993

1993

Earlier work this paper cites.

H. A. Castro, S. M. Tam, and M. A. Holler, “Implementation and performance of an analog nonvolatile neural network,” Analog Integrated Circuits and Signal Processing , vol. 4, no. 2, pp. 97–113, 1993

1993

Earlier work this paper cites.

S. Churcher, D. J. Baxter, A. Hamilton, A. F. Murray, and H. M. Reekie, “Generic analog neural computation-the epsilon chip,” in Advances in Neural Information Processing Systems , 1993, pp. 773–780

1993

Earlier work this paper cites.

J.-H. Shin, “Novel impulse neural circuits for pulsed neural network,” in Neural Networks, 1993. IJCNN’93-Nagoya. Proceedings of 1993 International Joint Conference on , vol. 3. IEEE, 1993, pp. 3017–3022

1993

Earlier work this paper cites.

J. G. Elias, “Artificial dendritic trees,” Neural Computation , vol. 5, no. 4, pp. 648–664, 1993

1993

Earlier work this paper cites.

M. Deyong, T. C. Eskridge, and C. Fields, “Temporal signal processing with high-speed hybrid analog-digital neural networks,” in Analog VLSI Neural Networks . Springer, 1993, pp. 105–126

1993

Earlier work this paper cites.

O. Fujita and Y. Amemiya, “A floating-gate analog memory device for neural networks,” Electron Devices, IEEE Transactions on , vol. 40, no. 11, pp. 2029–2035, 1993

1993

Earlier work this paper cites.

H. Ishiwara, “Proposal of adaptive-learning neuron circuits with ferroelectric analog-memory weights,” Japanese journal of applied physics , vol. 32, no. 1S, p. 442, 1993

1993

Earlier work this paper cites.

M. E. Nigri and P. C. Treleaven, “High level synthesis of neural network chips,” in New Trends in Neural Computation . Springer, 1993, pp. 448–453

1993

Earlier work this paper cites.

J. Lazzaro, J. Wawrzynek, M. Mahowald, M. Sivilotti, and D. Gillespie, “Silicon auditory processors as computer peripherals,” Neural Networks, IEEE Transactions on , vol. 4, no. 3, pp. 523–528, 1993

1993

Earlier work this paper cites.

H. P. Graf, E. Sackinger, and L. D. Jackel, “Recent developments of electronic neural nets in north america,” The Journal of VLSI Signal Processing , vol. 6, no. 1, pp. 19–31, 1993

1993

Earlier work this paper cites.

G. Cairns and L. Tarassenko, “Learning with analogue vlsp mlps,” in Microelectronics for Neural Networks and Fuzzy Systems, 1994., Proceedings of the Fourth International Conference on . IEEE, 1994, pp. 67–76

1994

Earlier work this paper cites.

V. Beiu, J. Peperstraete, J. Vandewalle, and R. Lauwereins, “Closse approximations of sigmoid functions by sum of step for vlsi implementation of neural networks,” Sci. Ann. Cuza Univ. , vol. 3, pp. 5–34, 1994

1994

Earlier work this paper cites.

J. Choi, B. J. Sheu, and J.-F. Chang, “A gaussian synapse circuit for analog vlsi neural networks,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol. 2, no. 1, pp. 129–133, 1994

1994

Earlier work this paper cites.

R. Coggins and M. A. Jabri, “Wattle: A trainable gain analogue vlsi neural network,” in Advances in Neural Information Processing Systems , 1994, pp. 874–881

1994

Earlier work this paper cites.

P. Masa, K. Hoen, and H. Wallinga, “A high-speed analog neural processor,” Micro, IEEE , vol. 14, no. 3, pp. 40–50, 1994

1994

Earlier work this paper cites.

A. J. Montalvo, R. S. Gyurcsik, and J. J. Paulos, “Building blocks for a temperature-compensated analog vlsi neural network with on-chip learning,” in Circuits and Systems, 1994. ISCAS’94., 1994 IEEE International Symposium on , vol. 6. IEEE, 1994, pp. 363–366

1994

Earlier work this paper cites.

——, “Analog cmos implementation of neural network for adaptive signal processing,” in Circuits and Systems, 1994. ISCAS’94., 1994 IEEE International Symposium on , vol. 6. IEEE, 1994, pp. 503–506

1994

Earlier work this paper cites.

K. Soelberg, R. L. Sigvartsen, T. S. Lande, and Y. Berg, “An analog continuous-time neural network,” Analog Integrated Circuits and Signal Processing , vol. 5, no. 3, pp. 235–246, 1994

1994

Earlier work this paper cites.

L.-Y. Song, A. Vannelli, and M. I. Elmasry, “A compact vlsi implementation of neural networks,” in VLSI Artificial Neural Networks Engineering . Springer, 1994, pp. 139–156

1994

Earlier work this paper cites.

M. Valle, D. D. Caviglia, and G. M. Bisio, “Back-propagation learning algorithms for analog vlsi implementation,” in VLSI for Neural Networks and Artificial Intelligence . Springer, 1994, pp. 35–44

1994

Earlier work this paper cites.

W. Fornaciari and F. Salice, “A low latency digital neural network architecture,” in VLSI for Neural Networks and Artificial Intelligence . Springer, 1994, pp. 81–91

1994

Earlier work this paper cites.

J. Cloutier and P. Y. Simard, “Hardware implementation of the backpropagation without multiplication,” in Microelectronics for Neural Networks and Fuzzy Systems, 1994., Proceedings of the Fourth International Conference on . IEEE, 1994, pp. 46–55

1994

Earlier work this paper cites.

Y. Kondo, Y. Koshiba, Y. Arima, M. Murasaki, T. Yamada, H. Amishiro, H. Shinohara, and H. Mori, “A 1.2 gflops neural network chip exhibiting fast convergence,” in Solid-State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC., 1994 IEEE International . IEEE, 1994, pp. 218–219

1994

Earlier work this paper cites.

G. Cardarilli, C. D’Alessandro, P. Marinucci, and F. Bordoni, “Vlsi implementation of a modular and programmable neural architecture,” in Microelectronics for Neural Networks and Fuzzy Systems, 1994., Proceedings of the Fourth International Conference on . IEEE, 1994, pp. 218–225

1994

Earlier work this paper cites.

P. Masa, K. Hoen, and H. Wallinga, “High speed vlsi neural network for high-energy physics,” in Microelectronics for Neural Networks and Fuzzy Systems, 1994., Proceedings of the Fourth International Conference on . IEEE, 1994, pp. 422–428

1994

Earlier work this paper cites.

G.-P. Economou, E. Mariatos, N. Economopoulos, D. Lymberopoulos, and C. Goutis, “Fpga implementation of artificial neural networks: an application on medical expert systems,” in Microelectronics for Neural Networks and Fuzzy Systems, 1994., Proceedings of the Fourth International Conference on . IEEE, 1994, pp. 287–293

1994

Earlier work this paper cites.

S. A. Guccione and M. J. Gonzalez, “A neural network implementation using reconfigurable architectures,” in Selected papers from the Oxford 1993 international workshop on field programmable logic and applications on More FPGAs, Oxford: Abingdon EE&CS Books , 1994, pp. 443–451

1994

Earlier work this paper cites.

V. Salapura, M. Gschwind, and O. Maischberger, “A fast fpga implementation of a general purpose neuron,” in Field-Programmable Logic Architectures, Synthesis and Applications . Springer, 1994, pp. 175–182

1994

Earlier work this paper cites.

J. G. Eldredge and B. L. Hutchings, “Density enhancement of a neural network using fpgas and run-time reconfiguration,” in FPGAs for Custom Computing Machines, 1994. Proceedings. IEEE Workshop on . IEEE, 1994, pp. 180–188

1994

Earlier work this paper cites.

N. M. Botros and M. Abdul-Aziz, “Hardware implementation of an artificial neural network using field programmable gate arrays (fpga’s),” IEEE Transactions on Industrial Electronics , vol. 41, no. 6, pp. 67–665, 1994

1994

Earlier work this paper cites.

J. Van der Spiegel, C. Donham, R. Etienne-Cummings, S. Fernando, P. Mueller, and D. Blackman, “Large scale analog neural computer with programmable architecture and programmable time constants for temporal pattern analysis,” in Neural Networks, 1994. IEEE World Congress on Computational Intelligence., 1994 IEEE International Conference on , vol. 3. IEEE, 1994, pp. 1830–1835

1994

Earlier work this paper cites.

M. Verleysen, P. Thissen, J.-L. Voz, and J. Madrenas, “An analog processor architecture for a neural network classifier,” Micro, IEEE , vol. 14, no. 3, pp. 16–28, 1994

1994

Earlier work this paper cites.

P. Maffezzoni and P. Gubian, “Vlsi design of radial functions hardware generator for neural computations,” in Microelectronics for Neural Networks and Fuzzy Systems, 1994., Proceedings of the Fourth International Conference on . IEEE, 1994, pp. 252–259

1994

Earlier work this paper cites.

S. Halgamuge, W. Poechmueller, C. Grimm, and M. Glesner, “Fuzzy interpretable dynamically developing neural networks with fpga based implementation,” in Microelectronics for Neural Networks and Fuzzy Systems, 1994., Proceedings of the Fourth International Conference on . IEEE, 1994, pp. 226–234

1994

Earlier work this paper cites.

G. Cauwenberghs, “A learning analog neural network chip with continuous-time recurrent dynamics,” Advances in Neural Information Processing Systems , pp. 858–858, 1994

1994

Earlier work this paper cites.

T. Morie and Y. Amemiya, “An all-analog expandable neural network lsi with on-chip backpropagation learning,” Solid-State Circuits, IEEE Journal of , vol. 29, no. 9, pp. 1086–1093, 1994

1994

Earlier work this paper cites.

H.-K. Yang, E. El-Masry et al. , “A cmos current-mode pwm technique for analog neural network implementations,” in Circuits and Systems, 1994. ISCAS’94., 1994 IEEE International Symposium on , vol. 6. IEEE, 1994, pp. 355–358

1994

Earlier work this paper cites.

K. V. Asari and C. Eswaran, “Systolic array implementation of artificial neural networks,” Microprocessors and Microsystems , vol. 18, no. 8, pp. 481–488, 1994

1994

Earlier work this paper cites.

W. Fornaciari and F. Salice, “An automatic vlsi implementation of hopfield anns,” in Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on , vol. 1. IEEE, 1994, pp. 499–502

1994

Earlier work this paper cites.

D. Reay, T. Green, and B. Williams, “Field programmable gate array implementation of a neural network accelerator,” in Hardware Implementation of Neural Networks and Fuzzy Logic, IEE Colloquium on . IET, 1994, pp. 2–1

1994

Earlier work this paper cites.

S. L. Bade and B. L. Hutchings, “Fpga-based stochastic neural networks-implementation,” in FPGAs for Custom Computing Machines, 1994. Proceedings. IEEE Workshop on . IEEE, 1994, pp. 189–198

1994

Earlier work this paper cites.

H. Pujol, J. Klein, E. Belhaire, and P. Garda, “Ra: An analog neurocomputer for the synchronous boltzmann machine,” in Microelectronics for Neural Networks and Fuzzy Systems, 1994., Proceedings of the Fourth International Conference on . IEEE, 1994, pp. 449–455

1994

Earlier work this paper cites.

H. C. Card, C. R. Schneider, and R. S. Schneider, “Learning capacitive weights in analog cmos neural networks,” Journal of VLSI signal processing systems for signal, image and video technology , vol. 8, no. 3, pp. 209–225, 1994

1994

Earlier work this paper cites.

P. Kinget and M. Steyaert, “Analogue cmos vlsi implementation of cellular neural networks with continuously programmable templates,” in Circuits and Systems, 1994. ISCAS’94., 1994 IEEE International Symposium on , vol. 6. IEEE, 1994, pp. 367–370

1994

Earlier work this paper cites.

P. W. Hollis and J. J. Paulos, “A neural network learning algorithm tailored for vlsi implementation,” Neural Networks, IEEE Transactions on , vol. 5, no. 5, pp. 784–791, 1994

1994

Earlier work this paper cites.

R. Woodburn, H. M. Reekie, and A. F. Murray, “Pulse-stream circuits for on-chip learning in analogue vlsi neural networks,” in Circuits and Systems, 1994. ISCAS’94., 1994 IEEE International Symposium on , vol. 4. IEEE, 1994, pp. 103–106

1994

Earlier work this paper cites.

P. Lysaght, J. Stockwood, J. Law, and D. Girma, “Artificial neural network implementation on a fine-grained fpga,” in Field-Programmable Logic Architectures, Synthesis and Applications . Springer, 1994, pp. 421–431

1994

Earlier work this paper cites.

T. Cornu and P. Ienne, “Performance of digital neuro-computers,” in Microelectronics for Neural Networks and Fuzzy Systems, 1994., Proceedings of the Fourth International Conference on . IEEE, 1994, pp. 87–93

1994

Earlier work this paper cites.

——, “On physical models of neural computation and their analog vlsi implementation,” in Physics and Computation, 1994. PhysComp’94, Proceedings., Workshop on . IEEE, 1994, pp. 255–264

1994

Earlier work this paper cites.

G. Indiveri and G. Bisio, “Analog subthreshold vlsi implementation of a neuromorphic model of the visual cortex for pre-attentive vision,” in Microelectronics for Neural Networks and Fuzzy Systems, 1994., Proceedings of the Fourth International Conference on . IEEE, 1994, pp. 439–448

1994

Earlier work this paper cites.

B. Linares-Barranco, E. Sánchez-Sinencio, A. Rodríguez-Vázquez, and J. L. Huertas, “Cmos analog neural network systems based on oscillatory neurons,” in Silicon Implementation of Pulse Coded Neural Networks . Springer, 1994, pp. 199–247

1994

Earlier work this paper cites.

R. Etienne-Cummings, C. Donham, J. Van der Spiegel, and P. Mueller, “Spatiotemporal computation with a general purpose analog neural computer: Real-time visual motion estimation,” in Neural Networks, 1994. IEEE World Congress on Computational Intelligence., 1994 IEEE International Conference on , vol. 3. IEEE, 1994, pp. 1836–1841

1994

Earlier work this paper cites.

D. Badoni, S. Bertazzoni, S. Buglioni, G. Salina, D. J. Amit, and S. Fusi, “Electronic implementation of an analog attractor neural network with stochastic learning,” NETWORK , 1994

1994

Earlier work this paper cites.

J. Ghosh, P. Lacour, and S. Jackson, “Ota-based neural network architectures with on-chip tuning of synapses,” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on , vol. 41, no. 1, pp. 49–58, 1994

1994

Earlier work this paper cites.

C. S. Ho, J. J. LlOU, M. GEORGIOPOULOS, G. L. HEILEMAN, and C. CHRISTODOULOU, “Analogue circuit design and implementation of an adaptive resonance theory (art) neural network architecture,” International Journal of Electronics , vol. 76, no. 2, pp. 271–291, 1994

1994

Earlier work this paper cites.

G. Jackson, A. Hamilton, and A. F. Murray, “The epsilon processor card: A framework for analog neural computation,” in Microelectronics for Neural Networks and Fuzzy Systems, 1994., Proceedings of the Fourth International Conference on . IEEE, 1994, pp. 280–286

1994

Earlier work this paper cites.

M. Onorato, M. Valle, D. Caviglia, and G. Bisio, “Non-linear circuit effects on analog vlsi neural network implementations,” in Microelectronics for Neural Networks and Fuzzy Systems, 1994., Proceedings of the Fourth International Conference on . IEEE, 1994, pp. 430–438

1994

Earlier work this paper cites.

L. Reyneri, H. Withagen, J. Hegt, and M. Chiaberge, “A comparison between analog and pulse stream vlsi hardware for neural networks and fuzzy systems,” in Microelectronics for Neural Networks and Fuzzy Systems, 1994., Proceedings of the Fourth International Conference on . IEEE, 1994, pp. 77–86

1994

Earlier work this paper cites.

N. Saxena and J. J. Clark, “A four-quadrant cmos analog multiplier for analog neural networks,” Solid-State Circuits, IEEE Journal of , vol. 29, no. 6, pp. 746–749, 1994

1994

Earlier work this paper cites.

X. Arreguit and E. Vittoz, “Perception systems implemented in analog vlsi for real-time applications,” in From Perception to Action Conference, 1994., Proceedings . IEEE, 1994, pp. 170–180

1994

Earlier work this paper cites.

M. A. Viredaz, C. Lehmann, F. Blayo, and P. Ienne, “Mantra: A multi-model neural-network computer,” in VLSI for Neural Networks and Artificial Intelligence . Springer, 1994, pp. 93–102

1994

Earlier work this paper cites.

——, “Silicon dendritic trees,” in Silicon Implementation of Pulse Coded Neural Networks . Springer, 1994, pp. 39–63

1994

Earlier work this paper cites.

M. DeYong and C. Fields, “Silicon neurons for phase and frequency detection and pattern generation,” in Silicon Implementation of Pulse Coded Neural Networks . Springer, 1994, pp. 65–77

1994

Earlier work this paper cites.

R. J. Douglas, M. A. Mahowald, and K. A. Martin, “Hybrid analog-digital architectures for neuromorphic systems,” in Neural Networks, 1994. IEEE World Congress on Computational Intelligence., 1994 IEEE International Conference on , vol. 3. IEEE, 1994, pp. 1848–1853

1994

Earlier work this paper cites.

B. Fowler and A. El Gamal, “Pulse-modulated analog neuron circuits,” Journal of VLSI signal processing systems for signal, image and video technology , vol. 8, no. 1, pp. 45–51, 1994

1994

Earlier work this paper cites.

L. Neiberg and D. Casasent, “High-capacity neural networks on nonideal hardware,” Applied optics , vol. 33, no. 32, pp. 7665–7675, 1994

1994

Earlier work this paper cites.

A. Mortara and E. A. Vittoz, “A communication architecture tailored for analog vlsi artificial neural networks: intrinsic performance and limitations,” Neural Networks, IEEE Transactions on , vol. 5, no. 3, pp. 459–466, 1994

1994

Earlier work this paper cites.

A. Achyuthan and M. I. Elmasry, “Mixed analog/digital hardware synthesis of artificial neural networks,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , vol. 13, no. 9, pp. 1073–1087, 1994

1994

Earlier work this paper cites.

——, “A design automation environment for mixed analog/digital anns,” in VLSI Artificial Neural Networks Engineering . Springer, 1994, pp. 91–137

1994

Earlier work this paper cites.

L. Prechelt et al. , “Proben1: A set of neural network benchmark problems and benchmarking rules,” 1994

1994

Earlier work this paper cites.

H. Card, B. Dolenko, D. McNeill, C. Schneider, and R. Schneider, “Is vlsi neural learning robust against circuit limitations?” in Neural Networks, 1994. IEEE World Congress on Computational Intelligence., 1994 IEEE International Conference on , vol. 3. IEEE, 1994, pp. 1889–1893

1994

Earlier work this paper cites.

M. Grattarola, M. Bove, S. Martinoia, and G. Massobrio, “Silicon neuron simulation with spice: tool for neurobiology and neural networks,” Medical and Biological Engineering and Computing , vol. 33, no. 4, pp. 533–536, 1995

1995

Earlier work this paper cites.

B. A. Minch, P. Hasler, C. Diorio, and C. Mead, “A silicon axon,” Advances in neural information processing systems , pp. 739–746, 1995

1995

Earlier work this paper cites.

A. Basaglia, W. Fornaciari, and F. Salice, “Correct implementation of digital neural networks,” in Circuits and Systems, 1995., Proceedings., Proceedings of the 38th Midwest Symposium on , vol. 1. IEEE, 1995, pp. 81–84

1995

Earlier work this paper cites.

S. Lee and K. Lau, “Low power building block for artificial neural networks,” Electronics Letters , vol. 31, no. 19, pp. 1618–1619, 1995

1995

Earlier work this paper cites.

P. Hasler, C. Diorio, B. A. Minch, and C. Mead, “Single transistor learning synapses,” Advances in neural information processing systems , pp. 817–826, 1995

1995

Earlier work this paper cites.

S. Lee and K. Lau, “An analog gaussian synapse for artificial neural networks,” in Circuits and Systems, 1995., Proceedings., Proceedings of the 38th Midwest Symposium on , vol. 1. IEEE, 1995, pp. 77–80

1995

Earlier work this paper cites.

B. A. Alhalabi and M. Bayoumi, “A scalable analog architecture for neural networks with on-chip learning and refreshing,” in VLSI, 1995. Proceedings., Fifth Great Lakes Symposium on . IEEE, 1995, pp. 33–38

1995

Earlier work this paper cites.

R. Coggins, M. Jabri, B. Flower, and S. Pickard, “A hybrid analog and digital vlsi neural network for intracardiac morphology classification,” Solid-State Circuits, IEEE Journal of , vol. 30, no. 5, pp. 542–550, 1995

1995

Earlier work this paper cites.

R. Coggins, M. A. Jabri, B. Flower, and S. Pickard, “Iceg morphology classification using an analogue vlsi neural network,” in Advances in Neural Information Processing Systems , 1995, pp. 731–738

1995

Earlier work this paper cites.

B. K. Dolenko and H. C. Card, “Tolerance to analog hardware of on-chip learning in backpropagation networks,” Neural Networks, IEEE Transactions on , vol. 6, no. 5, pp. 1045–1052, 1995

1995

Earlier work this paper cites.

S. M. Fakhraie, J. Xu, and K. Smith, “Design of cmos quadratic neural networks,” in Proc. IEEE Pacific Rim Conf. Communications, Computers, and Signal Processing , 1995, pp. 493–496

1995

Earlier work this paper cites.

J.-F. Lan and C.-Y. Wu, “Analog cmos current-mode implementation of the feedforward neural network with on-chip learning and storage,” in Neural Networks, 1995. Proceedings., IEEE International Conference on , vol. 1. IEEE, 1995, pp. 645–650

1995

Earlier work this paper cites.

T. Lindblad, C. Lindsey, F. Block, and A. Jayakumar, “Using software and hardware neural networks in a higgs search,” Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment , vol. 356, no. 2, pp. 498–506, 1995

1995

Earlier work this paper cites.

——, “A learning rule of neural networks via simultaneous perturbation and its hardware implementation,” Neural Networks , vol. 8, no. 2, pp. 251–259, 1995

1995

Earlier work this paper cites.

Y.-C. Kim and M. A. Shanblatt, “Architecture and statistical model of a pulse-mode digital multilayer neural network,” Neural Networks, IEEE Transactions on , vol. 6, no. 5, pp. 1109–1118, 1995

1995

Earlier work this paper cites.

——, “Random noise effects in pulse-mode digital multilayer neural networks,” Neural Networks, IEEE Transactions on , vol. 6, no. 1, pp. 220–229, 1995

1995

Earlier work this paper cites.

G. Cardarilli, G. Di Stefano, G. Fabrizi, and P. Marinucci, “Analysis and implementation of a vlsi neural network,” in Neural Networks, 1995. Proceedings., IEEE International Conference on , vol. 3. IEEE, 1995, pp. 1482–1486

1995

Earlier work this paper cites.

D. Johnson, J. Marsland, and W. Eccleston, “Neural network implementation using a single most per synapse,” Neural Networks, IEEE Transactions on , vol. 6, no. 4, pp. 1008–1011, 1995

1995

Earlier work this paper cites.

H. Hikawa, “Implementation of simplified multilayer neural networks with on-chip learning,” in Neural Networks, 1995. Proceedings., IEEE International Conference on , vol. 4. IEEE, 1995, pp. 1633–1637

1995

Earlier work this paper cites.

S. R. Hasan and N. K. Siong, “A vlsi bam neural network chip for pattern recognition applications,” in Neural Networks, 1995. Proceedings., IEEE International Conference on , vol. 1. IEEE, 1995, pp. 164–168

1995

Earlier work this paper cites.

A. Torralba, F. Colodro, E. Ibanez, and L. G. Franquelo, “Two digital circuits for a fully parallel stochastic neural network,” Neural Networks, IEEE Transactions on , vol. 6, no. 5, pp. 1264–1268, 1995

1995

Earlier work this paper cites.

P. Kinget and M. S. Steyaert, “A programmable analog cellular neural network cmos chip for high speed image processing,” IEEE Journal of Solid-State Circuits , vol. 30, no. 3, pp. 235–243, 1995

1995

Earlier work this paper cites.

S. Kondo, T. Shibata, and T. Ohmi, “Superior generalization capability of hardware-learing algorithm developed for self-learning neuron-mos neural networks,” Japanese journal of applied physics , vol. 34, no. 2S, p. 1066, 1995

1995

Earlier work this paper cites.

V. Petridis and K. Paraschidis, “On the properties of the feedforward method: A simple training law for on-chip learning,” Neural Networks, IEEE Transactions on , vol. 6, no. 6, pp. 1536–1541, 1995

1995

Earlier work this paper cites.

S. R. Schultz and M. A. Jabri, “A silicon basis for synaptic plasticity,” Neural Processing Letters , vol. 2, no. 6, pp. 23–27, 1995

1995

Earlier work this paper cites.

F. J. Pelayo, E. Ros, P. Martin-Smith, F. Fernández, and A. Prieto, “A vlsi approach to the implementation of additive and shunting neural networks,” in From Natural to Artificial Neural Computation . Springer, 1995, pp. 728–735

1995

Earlier work this paper cites.

A. G. Andreou, R. C. Meitzler, K. Strohbehn, and K. Boahen, “Analog vlsi neuromorphic image acquisition and pre-processing systems,” Neural Networks , vol. 8, no. 7, pp. 1323–1347, 1995

1995

Earlier work this paper cites.

H. P. Graf, C. R. Nohl, and J. Ben, “Image recognition with an analog neural net chip,” Machine vision and applications , vol. 8, no. 2, pp. 131–140, 1995

1995

Earlier work this paper cites.

J. G. Elias and D. P. Northmore, “Switched-capacitor neuromorphs with wide-range variable dynamics,” Neural Networks, IEEE Transactions on , vol. 6, no. 6, pp. 1542–1548, 1995

1995

Earlier work this paper cites.

——, “Vlsi neuromorphs: Building blocks for neural circuits,” in The Neurobiology of Computation . Springer, 1995, pp. 385–390

1995

Earlier work this paper cites.

H. Kosaka, T. Shibata, H. Ishii, and T. Ohmi, “An excellent weight-updating-linearity eeprom synapse memory cell for self-learning neuron-mos neural networks,” Electron Devices, IEEE Transactions on , vol. 42, no. 1, pp. 135–143, 1995

1995

Earlier work this paper cites.

T. Shibata, H. Kosaka, H. Ishii, and T. Ohmi, “A neuron-mos neural network using self-learning-compatible synapse circuits,” Solid-State Circuits, IEEE Journal of , vol. 30, no. 8, pp. 913–922, 1995

1995

Earlier work this paper cites.

A. Mortara, E. A. Vittoz, and P. Venier, “A communication scheme for analog vlsi perceptive systems,” Solid-State Circuits, IEEE Journal of , vol. 30, no. 6, pp. 660–669, 1995

1995

Earlier work this paper cites.

R. Douglas, M. Mahowald, and C. Mead, “Neuromorphic analogue vlsi,” Annual review of neuroscience , vol. 18, pp. 255–281, 1995

1995

Earlier work this paper cites.

G. Indiveri, L. Raffo, S. P. Sabatini, and G. M. Bisio, “A neuromorphic architecture for cortical multilayer integration of early visual tasks,” Machine vision and applications , vol. 8, no. 5, pp. 305–314, 1995

1995

Earlier work this paper cites.

B. J. Sheu and J. Choi, “Design methodologies of vlsi neural networks,” in Neural Information Processing and VLSI . Springer, 1995, pp. 185–220

1995

Earlier work this paper cites.

G. Grossi, R. Posenato, M. Costa et al. , “Fast prototyping for hardware neural networks,” 1995

1995

Earlier work this paper cites.

H. Bolouri, P. Morgan, and C. Peacock, “A ram-based neural network architecture for wafer scale integration,” in Proc. IEEE Int. Conf. on Wafer Scale Integration (San Francisco) . Citeseer, 1995, pp. 82–90

1995

Earlier work this paper cites.

V. Beiu and J. G. Taylor, “Optimal mapping of neural networks onto fpgas,” in From Natural to Artificial Neural Computation . Springer, 1995, pp. 822–829

1995

Earlier work this paper cites.

H. C. Card, D. K. McNeill, C. R. Schneider, and R. S. Schneider, “The impact of vlsi fabrication on neural learning,” in Circuits and Systems, 1995. ISCAS’95., 1995 IEEE International Symposium on , vol. 2. IEEE, 1995, pp. 985–988

1995

Earlier work this paper cites.

D. Dupeyron, S. Le Masson, Y. Deval, G. Le Masson, and J.-P. Dom, “A bicmos implementation of the hodgkin-huxley formalism,” in Microelectronics for Neural Networks, 1996., Proceedings of Fifth International Conference on . IEEE, 1996, pp. 311–316

1996

Earlier work this paper cites.

S. Wolpert and E. Micheli-Tzanakou, “A neuromime in vlsi,” Neural Networks, IEEE Transactions on , vol. 7, no. 2, pp. 300–306, 1996

1996

Earlier work this paper cites.

T. Yamakawa, “Silicon implementation of a fuzzy neuron,” Fuzzy Systems, IEEE Transactions on , vol. 4, no. 4, pp. 488–501, 1996

1996

Earlier work this paper cites.

C. Diorio, P. Hasler, B. A. Minch, and C. A. Mead, “A single-transistor silicon synapse,” Electron Devices, IEEE Transactions on , vol. 43, no. 11, pp. 1972–1980, 1996

1996

Earlier work this paper cites.

A. Almeida and J. Franca, “Digitally programmable analog building blocks for the implementation of artificial neural networks,” Neural Networks, IEEE Transactions on , vol. 7, no. 2, pp. 506–514, 1996

1996

Earlier work this paper cites.

Y. Berg, R. L. Sigvartsen, T. S. Lande, and A. Abusland, “An analog feed-forward neural network with on-chip learning,” Analog Integrated Circuits and Signal Processing , vol. 9, no. 1, pp. 65–75, 1996

1996

Earlier work this paper cites.

G. Bo, D. Caviglia, and M. Valle, “A current mode cmos multi-layer perceptron chip,” in Microelectronics for Neural Networks, 1996., Proceedings of Fifth International Conference on . IEEE, 1996, pp. 103–106

1996

Earlier work this paper cites.

R. C. Chang, B. J. Sheu, J. Choi, and D. C.-H. Chen, “Programmable-weight building blocks for analog vlsi neural network processors,” Analog Integrated Circuits and Signal Processing , vol. 9, no. 3, pp. 215–230, 1996

1996

Earlier work this paper cites.

J.-W. Cho, “Modular neuro-chip with on-chip learning and adjustable learning parameters,” Neural Processing Letters , vol. 4, no. 1, pp. 45–52, 1996

1996

Earlier work this paper cites.

Y. K. Choi, K.-H. Ahn, and S.-Y. Lee, “Effects of multiplier output offsets on on-chip learning for analog neuro-chips,” Neural Processing Letters , vol. 4, no. 1, pp. 1–8, 1996

1996

Earlier work this paper cites.

D. Coue and G. Wilson, “A four-quadrant subthreshold mode multiplier for analog neural-network applications,” Neural Networks, IEEE Transactions on , vol. 7, no. 5, pp. 1212–1219, 1996

1996

Earlier work this paper cites.

——, “An experimental analog vlsi neural network with on-chip back-propagation learning,” Analog Integrated Circuits and Signal Processing , vol. 9, no. 3, pp. 231–245, 1996

1996

Earlier work this paper cites.

T. Yildirim and J. S. Marsland, “A conic section function network synapse and neuron implementation in vlsi hardware,” in Neural Networks, 1996., IEEE International Conference on , vol. 2. IEEE, 1996, pp. 974–979

1996

Earlier work this paper cites.

S. Kumar, K. Forward, and M. Palaniswami, “Performance evaluation of a risc neuro-processor for neural networks,” in High Performance Computing, 1996. Proceedings. 3rd International Conference on . IEEE, 1996, pp. 351–356

1996

Earlier work this paper cites.

L. Larsson, S. Krol, and K. Lagemann, “Neneb-an application adjustable single chip neural network processor for mobile real time image processing,” in Neural Networks for Identification, Control, Robotics, and Signal/Image Processing, 1996. Proceedings., International Workshop on . IEEE, 1996, pp. 154–162

1996

Earlier work this paper cites.

K. Aihara, O. Fujita, and K. Uchimura, “A digital neural network lsi using sparse memory access architecture,” in Microelectronics for Neural Networks, 1996., Proceedings of Fifth International Conference on . IEEE, 1996, pp. 139–148

1996

Earlier work this paper cites.

N. Avellana, A. Strey, R. Holgado, J. A. Fernandes, R. Capillas, and E. Valderrama, “Design of a low-cost and high-speed neurocomputer system,” in Microelectronics for Neural Networks, 1996., Proceedings of Fifth International Conference on . IEEE, 1996, pp. 221–226

1996

Earlier work this paper cites.

J.-C. Bor and C.-Y. Wu, “Pulse-width-modulation feedforward neural network design with on-chip learning,” in Circuits and Systems, 1996., IEEE Asia Pacific Conference on . IEEE, 1996, pp. 369–372

1996

Earlier work this paper cites.

H. Djahanshahi, M. Ahmadi, G. Jullien, and W. Miller, “A unified synapse-neuron building block for hybrid vlsi neural networks,” in Circuits and Systems, 1996. ISCAS’96., Connecting the World., 1996 IEEE International Symposium on , vol. 3. IEEE, 1996, pp. 483–486

1996

Earlier work this paper cites.

——, “A modular architecture for hybrid vlsi neural networks and its application in a smart photosensor,” in Neural Networks, 1996., IEEE International Conference on , vol. 2. IEEE, 1996, pp. 868–873

1996

Earlier work this paper cites.

H. Djahanshahi, M. Ahmadi, G. A. Jullien, and W. C. Miller, “Design and vlsi implementation of a unified synapse-neuron architecture,” in VLSI, 1996. Proceedings., Sixth Great Lakes Symposium on . IEEE, 1996, pp. 228–233

1996

Earlier work this paper cites.

T. Lehmann, E. Bruun, and C. Dietrich, “Mixed analog/digital matrix-vector multiplier for neural network synapses,” Analog Integrated Circuits and Signal Processing , vol. 9, no. 1, pp. 55–63, 1996

1996

Earlier work this paper cites.

A. Pérez-Uribe and E. Sanchez, “Fpga implementation of an adaptable-size neural network,” in Artificial Neural Networks?ICANN 96 . Springer, 1996, pp. 383–388

1996

Earlier work this paper cites.

B. Girau and A. Tisserand, “On-line arithmetic-based reprogrammable hardware implementation of multilayer perceptron back-propagation,” in microneuro . IEEE, 1996, p. 168

1996

Earlier work this paper cites.

R. Dogaru, A. Murgan, S. Ortmann, and M. Glesner, “A modified rbf neural network for efficient current-mode vlsi implementation,” in Microelectronics for Neural Networks, 1996., Proceedings of Fifth International Conference on . IEEE, 1996, pp. 265–270

1996

Earlier work this paper cites.

——, “An analog vlsi recurrent neural network learning a continuous-time trajectory,” Neural Networks, IEEE Transactions on , vol. 7, no. 2, pp. 346–361, 1996

1996

Earlier work this paper cites.

——, “Adaptation, learning and storage in analog vlsi,” in ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International . IEEE, 1996, pp. 273–278

1996

Earlier work this paper cites.

Y. Ota and B. M. Wilamowski, “Cmos implementation of a pulse-coded neural network with a current controlled oscillator,” in IEEE International Symposium on Circuits and Systems , 1996, pp. III–410

1996

Earlier work this paper cites.

L. Chen, M. Wedlake, G. Deliyannides, and H. Kwok, “Hybrid architecture for analogue neural network and its circuit implementation,” in Circuits, Devices and Systems, IEE Proceedings- , vol. 143, no. 2. IET, 1996, pp. 123–128

1996

Earlier work this paper cites.

M. Gschwind, V. Salapura, and O. Maischberger, “A generic building block for hopfield neural networks with on-chip learning,” in IEEE International Symposium on Circuits and Systems, Atlanta, GA . Citeseer, 1996

1996

Earlier work this paper cites.

C.-Y. Wu and J.-F. Lan, “Cmos current-mode neural associative memory design with on-chip learning,” Neural Networks, IEEE Transactions on , vol. 7, no. 1, pp. 167–181, 1996

1996

Earlier work this paper cites.

M. Rossmann, B. Hesse, K. Goser, A. Buhlmeier, and G. Manteuffel, “Implementation of a biologically inspired neuron-model in fpga,” in Microelectronics for Neural Networks, 1996., Proceedings of Fifth International Conference on . IEEE, 1996, pp. 322–329

1996

Earlier work this paper cites.

A. Bühlmeier, G. Manteuffel, M. Rossmann, and K. Goser, “Robot learning in analog neural hardware,” in Artificial Neural Networks?ICANN 96 . Springer, 1996, pp. 311–316

1996

Earlier work this paper cites.

M. Conti, G. Guaitini, and C. Turchetti, “An analog cmos neural network with on-chip learning and multilevel weight storage,” Artificial Neural Networks?ICANN 96 , pp. 761–766, 1996

1996

Earlier work this paper cites.

T. Serrano-Gotarredona and B. Linares-Barranco, “A real-time clustering microchip neural engine,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol. 4, no. 2, pp. 195–209, 1996

1996

Earlier work this paper cites.

G. Wilson, “Cmos subthreshold-mode i/v converter for analogue neural network applications,” Electronics Letters , vol. 32, no. 11, pp. 990–991, 1996

1996

Earlier work this paper cites.

B. M. Wilamowski, Y. Ota, and M. L. Padgett, “Cmos realization of a pulse-stream artificial neural network using a current controlled oscillator,” in World Congr. Neural Networks , 1996, pp. 1317–1320

1996

Earlier work this paper cites.

R. Yentis Jr and M. Zaghloul, “Vlsi implementation of locally connected neural network for solving partial differential equations,” Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on , vol. 43, no. 8, pp. 687–690, 1996

1996

Earlier work this paper cites.

T. Zahn, R. Izak, and K. Trott, “Mixed analog-digital neurochip for acoustical attention,” Graduiertenkolleg ?Informatik und Technik?, TU Ilmenau , 1996

1996

Earlier work this paper cites.

V. Fabbrizio, F. Raynal, X. Mariaud, A. Kramer, and G. Colli, “Low power, low voltage conductance-mode cmos analog neuron,” in Microelectronics for Neural Networks, 1996., Proceedings of Fifth International Conference on . IEEE, 1996, pp. 111–115

1996

Earlier work this paper cites.

A. Van Schaik, E. Fragnière, and E. Vittoz, “An analogue electronic model of ventral cochlear nucleus neurons,” in Microelectronics for Neural Networks, 1996., Proceedings of Fifth International Conference on . IEEE, 1996, pp. 52–59

1996

Earlier work this paper cites.

V. Roychowdhury, D. Janes, S. Bandyopadhyay, and X. Wang, “Collective computational activity in self-assembled arrays of quantum dots: a novel neuromorphic architecture for nanoelectronics,” Electron Devices, IEEE Transactions on , vol. 43, no. 10, pp. 1688–1699, 1996

1996

Earlier work this paper cites.

——, “Direct synthesis of neural networks,” in Microelectronics for Neural Networks, 1996., Proceedings of Fifth International Conference on . IEEE, 1996, pp. 257–264

1996

Earlier work this paper cites.

K. Kollmann, K.-R. Riemschneider, and H. C. Zeidler, “On-chip backpropagation training using parallel stochastic bit streams,” in Microelectronics for Neural Networks, 1996., Proceedings of Fifth International Conference on . IEEE, 1996, pp. 149–156

1996

Earlier work this paper cites.

M. PARODI and M. STORACE, “On a circuit representation of the hodgkin and huxley nerve axon membrane equations,” International journal of circuit theory and applications , vol. 25, no. 2, pp. 115–124, 1997

1997

Earlier work this paper cites.

F. Pelayo, E. Ros, X. Arreguit, and A. Prieto, “Vlsi implementation of a neural model using spikes,” Analog Integrated Circuits and Signal Processing , vol. 13, no. 1-2, pp. 111–121, 1997

1997

Earlier work this paper cites.

G. Patel and S. DeWeerth, “Analogue vlsi morris-lecar neuron,” Electronics letters , vol. 33, no. 12, pp. 997–998, 1997

1997

Earlier work this paper cites.

M. Mattia and S. Fusi, “Modeling networks with vlsi (linear) integrate-and-fire neurons,” in Losanna, Switzerland: Proceedings of the 7th international conference on artificial neural networks . Citeseer, 1997

1997

Earlier work this paper cites.

C. Cerkez, I. Aybay, and U. Halici, “A digital neuron realization for the random neural network model,” in Neural Networks, 1997., International Conference on , vol. 2. IEEE, 1997, pp. 1000–1004

1997

Earlier work this paper cites.

K. Al-Ruwaihi, “Cmos analogue neurone circuit with programmable activation functions utilising mos transistors with optimised process/device parameters,” IEE Proceedings-Circuits, Devices and Systems , vol. 144, no. 6, pp. 318–322, 1997

1997

Earlier work this paper cites.

K. Lau and S. Lee, “A programmable cmos gaussian synapse for analogue vlsi neural networks,” International journal of electronics , vol. 83, no. 1, pp. 91–98, 1997

1997

Earlier work this paper cites.

P. Häfliger, M. Mahowald, and L. Watts, “A spike based learning neuron in analog vlsi,” in Advances in neural information processing systems , 1997, pp. 692–698

1997

Earlier work this paper cites.

P. H. M. Mahowald and L. Watts, “A spike based learning neuron in analog vlsi,” Advances in Neural Information Processing Systems , vol. 9, p. 692, 1997

1997

Earlier work this paper cites.

G. Bo, D. Caviglia, M. Valle, R. Stratta, and E. Trucco, “A reconfigurable analog vlsi neural network architecture with non linear synapses,” in Neural Nets WIRN VIETRI-96 . Springer, 1997, pp. 281–288

1997

Earlier work this paper cites.

G. Bollano, M. Costa, D. Palmisano, and E. Pasero, “Off-chip training of analog hardware feed-forward neural networks through hyper-floating resilient propagation,” in Neural Nets WIRN VIETRI-96 . Springer, 1997, pp. 289–297

1997

Earlier work this paper cites.

E. El-Masry, H.-K. Yang, M. Yakout et al. , “Implementations of artificial neural networks using current-mode pulse width modulation technique,” Neural Networks, IEEE Transactions on , vol. 8, no. 3, pp. 532–548, 1997

1997

Earlier work this paper cites.

——, “An analog vlsi neural network with on-chip perturbation learning,” Solid-State Circuits, IEEE Journal of , vol. 32, no. 4, pp. 535–543, 1997

1997

Earlier work this paper cites.

——, “Toward a general-purpose analog vlsi neural network with on-chip learning,” Neural Networks, IEEE Transactions on , vol. 8, no. 2, pp. 413–423, 1997

1997

Earlier work this paper cites.

C. Tang and H. Kwan, “Digital implementation of neural networks with quantized neurons,” in Circuits and Systems, 1997. ISCAS’97., Proceedings of 1997 IEEE International Symposium on , vol. 1. IEEE, 1997, pp. 649–652

1997

Earlier work this paper cites.

H. Djahanshahi, M. Ahmadi, G. Jullien, and W. Miller, “A self-scaling neural hardware structure that reduces the effect of some implementation errors,” in Neural Networks for Signal Processing [1997] VII. Proceedings of the 1997 IEEE Workshop . IEEE, 1997, pp. 588–597

1997

Earlier work this paper cites.

H. Djahanshahi, M. Ahmadi, G. A. Jullien, and W. C. Miller, “Neural network integrated circuits with single-block mixed-signal arrays,” in Signals, Systems & Computers, 1997. Conference Record of the Thirty-First Asilomar Conference on , vol. 2. IEEE, 1997, pp. 1130–1135

1997

Earlier work this paper cites.

K. Watanabe, L. Wang, H.-W. Cha, and S. Ogawa, “A current-mode approach to cmos neural network implementation,” in Algorithms and Architectures for Parallel Processing, 1997. ICAPP 97., 1997 3rd International Conference on . IEEE, 1997, pp. 625–637

1997

Earlier work this paper cites.

J. Blake, L. Maguire, T. McGinnity, and L. McDaid, “Using xilinx fpgas to implement neural networks and fuzzy systems,” in Neural and Fuzzy Systems: Design, Hardware and Applications (Digest No: 1997/133), IEE Colloquium on . IET, 1997, pp. 1–1

1997

Earlier work this paper cites.

T. Kamio, H. Adachi, H. Ninomiya, and H. Asai, “A design method of dwt analog neuro chip for vlsi implementation,” in Instrumentation and Measurement Technology Conference, 1997. IMTC/97. Proceedings. Sensing, Processing, Networking., IEEE , vol. 2. IEEE, 1997, pp. 1210–1214

1997

Earlier work this paper cites.

M. Rossmann, A. Bühlmeier, G. Manteuffel, and K. Goser, “short-and long-term dynamics in a stochastic pulse stream neuron implemented in fpga,” in Artificial Neural Networks?ICANN’97 . Springer, 1997, pp. 1241–1246

1997

Earlier work this paper cites.

P. J. Murtagh and A. C. Tsoi, “A reconfigurable bit-serial vlsi systolic array neuro-chip,” Journal of Parallel and Distributed Computing , vol. 44, no. 1, pp. 53–70, 1997

1997

Earlier work this paper cites.

J.-S. Ker, Y.-H. Kuo, R.-C. Wen, and B.-D. Liu, “Hardware implementation of cmac neural network with reduced storage requirement,” Neural Networks, IEEE Transactions on , vol. 8, no. 6, pp. 1545–1556, 1997

1997

Earlier work this paper cites.

D. Zhang and M. I. Elmasry, “Vlsi compressor design with applications to digital neural networks,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol. 5, no. 2, pp. 230–233, 1997

1997

Earlier work this paper cites.

A. Laflaquiere, S. L. Masson, J. P. Dom, and G. L. Masson, “Accurate analog vlsi model of calcium-dependent bursting neurons,” in Neural Networks,1997., International Conference on , vol. 2, Jun 1997, pp. 882–887 vol.2

1997

Earlier work this paper cites.

R. Damle, V. Rao, and F. Kern, “Robust control of smart structures using neural network hardware,” Smart materials and structures , vol. 6, no. 3, p. 301, 1997

1997

Earlier work this paper cites.

G. Indiveri and P. Verschure, “Autonomous vehicle guidance using analog vlsi neuromorphic sensors,” in Artificial Neural Networks?ICANN’97 . Springer, 1997, pp. 811–816

1997

Earlier work this paper cites.

F. N. Sibai and S. D. Kulkarni, “A time-multiplexed reconfigurable neuroprocessor,” IEEE Micro , vol. 17, no. 1, pp. 58–65, 1997

1997

Earlier work this paper cites.

C. Diorio, P. Hasler, B. A. Minch, and C. A. Mead, “A floating-gate mos learning array with locally computed weight updates,” Electron Devices, IEEE Transactions on , vol. 44, no. 12, pp. 2281–2289, 1997

1997

Earlier work this paper cites.

C. Diorio, P. Hasler, B. A. Minch, and C. Mead, “A complementary pair of four-terminal silicon synapses,” Analog Integrated Circuits and Signal Processing , vol. 13, no. 1-2, pp. 153–166, 1997

1997

Earlier work this paper cites.

C. Rasche, R. Douglas, and M. Mahowald, “Characterization of a silicon pyramidal neuron,” PROGRESS IN NEURAL PROCESSING , pp. 169–177, 1998

1998

Earlier work this paper cites.

M. F. Simoni and S. P. DeWeerth, “Adaptation in an avlsi model of a neuron,” in Circuits and Systems, 1998. ISCAS’98. Proceedings of the 1998 IEEE International Symposium on , vol. 3. IEEE, 1998, pp. 111–114

1998

Earlier work this paper cites.

C. Toumazou, J. Georgiou, and E. Drakakis, “Current-mode analogue circuit representation of hodgkin and huxley neuron equations,” Electronics Letters , vol. 34, no. 14, pp. 1376–1377, 1998

1998

Earlier work this paper cites.

V. Bohossian, P. Hasler, and J. Bruck, “Programmable neural logic,” Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on , vol. 21, no. 4, pp. 346–351, 1998

1998

Earlier work this paper cites.

V. Varshavsky, “Cmos artificial neuron on the base of β \beta -driven threshold element,” in Systems, Man, and Cybernetics, 1998. 1998 IEEE International Conference on , vol. 2. IEEE, 1998, pp. 1857–1861

1998

Earlier work this paper cites.

M. Al-Nsour and H. S. Abdel-Aty-Zohdy, “Implementation of programmable digital sigmoid function circuit for neuro-computing,” in Circuits and Systems, 1998. Proceedings. 1998 Midwest Symposium on . IEEE, 1998, pp. 571–574

1998

Earlier work this paper cites.

T. McGinnity, B. Roche, L. Maguire, and L. McDaid, “Novel architecture and synapse design for hardware implementations of neural networks,” Computers & electrical engineering , vol. 24, no. 1, pp. 75–87, 1998

1998

Earlier work this paper cites.

M. Annunziato, D. Badoni, S. Fusi, and A. Salamon, “Analog vlsi implementation of a spike driven stochastic dynamical synapse,” in ICANN 98 . Springer, 1998, pp. 475–480

1998

Earlier work this paper cites.

M. A. Glover, A. Hamilton, and L. S. Smith, “An analog vlsi integrate-and-fire neural network for sound segmentation.” in NC , 1998, pp. 86–92

1998

Earlier work this paper cites.

L. S. Smith and A. Hamilton, Neuromorphic systems: engineering silicon from neurobiology . World Scientific, 1998, vol. 10

1998

Earlier work this paper cites.

A. Abutalebi and S. Fakhraie, “A submicron analog neural network with an adjustable-level output unit,” in Microelectronics, 1998. ICM’98. Proceedings of the Tenth International Conference on . IEEE, 1998, pp. 294–297

1998

Earlier work this paper cites.

J.-W. Cho and S.-Y. Lee, “Analog neuro-chips with on-chip learning capability for adaptive nonlinear equalizers,” in Neural Networks Proceedings, 1998. IEEE World Congress on Computational Intelligence. The 1998 IEEE International Joint Conference on , vol. 1. IEEE, 1998, pp. 581–586

1998

Earlier work this paper cites.

O. Saito, K. Aihara, O. Fujita, and K. Uchimura, “A 1m synapse self-learning digital neural network chip,” in Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International . IEEE, 1998, pp. 94–95

1998

Earlier work this paper cites.

J. Blake, L. P. Maguire, T. McGinnity, B. Roche, and L. McDaid, “The implementation of fuzzy systems, neural networks and fuzzy neural networks using fpgas,” Information Sciences , vol. 112, no. 1, pp. 151–168, 1998

1998

Earlier work this paper cites.

J.-L. Beuchat, J.-O. Haenni, and E. Sanchez, “Hardware reconfigurable neural networks,” in Parallel and Distributed Processing . Springer, 1998, pp. 91–98

1998

Earlier work this paper cites.

J.-L. Beuchat and E. Sanchez, “A reconfigurable neuroprocessor with on-chip pruning,” in ICANN 98 . Springer, 1998, pp. 1159–1164

1998

Earlier work this paper cites.

Y.-C. Kim, D.-K. Kang, and T.-W. Lee, “Risc-based coprocessor with a dedicated vlsi neural network,” in Electronics, Circuits and Systems, 1998 IEEE International Conference on , vol. 3. IEEE, 1998, pp. 281–283

1998

Earlier work this paper cites.

Y. Taright and M. Hubin, “Fpga implementation of a multilayer perceptron neural network using vhdl,” in Signal Processing Proceedings, 1998. ICSP’98. 1998 Fourth International Conference on , vol. 2. IEEE, 1998, pp. 1311–1314

1998

Earlier work this paper cites.

M. Figueiredo, C. Gloster et al. , “Implementation of a probabilistic neural network for multi-spectral image classification on an fpga based custom computing machine,” in Neural Networks, 1998. Proceedings. Vth Brazilian Symposium on . IEEE, 1998, pp. 174–179

1998

Earlier work this paper cites.

D. Abramson, K. Smith, P. Logothetis, and D. Duke, “Fpga based implementation of a hopfield neural network for solving constraint satisfaction problems,” in Euromicro Conference, 1998. Proceedings. 24th , vol. 2. IEEE, 1998, pp. 688–693

1998

Earlier work this paper cites.

P. Del Giudice, S. Fusi, D. Badoni, V. Dante, and D. J. Amit, “Learning attractors in an asynchronous, stochastic electronic neural network,” Network: Computation in Neural Systems , vol. 9, no. 2, pp. 183–205, 1998

1998

Earlier work this paper cites.

——, “A 16 × \times 16 cellular neural network universal chip: The first complete single-chip dynamic computer array with distributed memory and with gray-scale input-output,” Analog Integrated Circuits and Signal Processing , vol. 15, no. 3, pp. 227–237, 1998

1998

Earlier work this paper cites.

T. Schoenauer, N. Mehrtash, and H. Klar, “Architecture of a neuroprocessor chip for pulse-coded neural networks,” in International Conference on Computational Intelligence and Neuroscience (ICCIN’98),(JCIS’98) . Citeseer, 1998, pp. 17–20

1998

Earlier work this paper cites.

T. G. Morris, T. K. Horiuchi, and S. P. DeWeerth, “Object-based selection within an analog vlsi visual attention system,” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on , vol. 45, no. 12, pp. 1564–1572, 1998

1998

Earlier work this paper cites.

P. Martins Engel and R. F. Molz, “A new proposal for implementation of competitive neural networks in analog hardware,” in Neural Networks, 1998. Proceedings. Vth Brazilian Symposium on . IEEE, 1998, pp. 186–191

1998

Earlier work this paper cites.

T. Morris and S. DeWeerth, “Analog vlsi excitatory feedback circuits for attentional shifts and tracking,” in Neuromorphic systems engineering . Springer, 1998, pp. 151–174

1998

Earlier work this paper cites.

——, “Floating-gate mos synapse transistors,” in Neuromorphic systems engineering . Springer, 1998, pp. 315–337

1998

Earlier work this paper cites.

P. Hasler, C. Diorio, and B. A. Minch, “A four-quadrant floating-gate synapse,” in Circuits and Systems, 1998. ISCAS’98. Proceedings of the 1998 IEEE International Symposium on , vol. 3. IEEE, 1998, pp. 29–32

1998

Earlier work this paper cites.

K. A. Boahen, “Communicating neuronal ensembles between neuromorphic chips,” in Neuromorphic systems engineering . Springer, 1998, pp. 229–259

1998

Earlier work this paper cites.

J. Ryan, M.-J. Lin, and R. Miikkulainen, “Intrusion detection with neural networks,” Advances in neural information processing systems , pp. 943–949, 1998

1998

Earlier work this paper cites.

J. Kramer and G. Indiveri, “Neuromorphic vision sensors and preprocessors in system applications,” in SYBEN-Broadband European Networks and Electronic Image Capture and Publishing . International Society for Optics and Photonics, 1998, pp. 134–146

1998

Earlier work this paper cites.

Y. LeCun, C. Cortes, and C. J. Burges, “The mnist database of handwritten digits,” 1998

1998

Earlier work this paper cites.

S. Draghici, “Using information entropy bounds to design vlsi friendly neural networks,” in Neural Networks Proceedings, 1998. IEEE World Congress on Computational Intelligence. The 1998 IEEE International Joint Conference on , vol. 1. IEEE, 1998, pp. 547–552

1998

Earlier work this paper cites.

——, “On the complexity of vlsi-friendly neural networks for classification problems,” in Advances in Artificial Intelligence . Springer, 1998, pp. 285–297

1998

Earlier work this paper cites.

C. Blake and C. J. Merz, “ { \{ UCI } \} repository of machine learning databases,” 1998

1998

Earlier work this paper cites.

S. Le Masson, A. Laflaquiere, T. Bal, and G. Le Masson, “Analog circuits for modeling biological neural networks: design and applications,” Biomedical Engineering, IEEE Transactions on , vol. 46, no. 6, pp. 638–645, 1999

1999

Earlier work this paper cites.

J. Shin and C. Koch, “Dynamic range and sensitivity adaptation in a silicon spiking neuron,” Neural Networks, IEEE Transactions on , vol. 10, no. 5, pp. 1232–1238, 1999

1999

Earlier work this paper cites.

S. Draghici, D. Miller et al. , “A vlsi neural network classifier based on integer-valued weights,” in Neural Networks, 1999. IJCNN’99. International Joint Conference on , vol. 4. IEEE, 1999, pp. 2419–2424

1999

Earlier work this paper cites.

V. Varshavsky and V. Marakhovsky, “Learning experiments with cmos artificial neuron,” in Computational Intelligence . Springer, 1999, pp. 706–707

1999

Earlier work this paper cites.

——, “Beta-cmos artificial neuron and implementability limits,” in Engineering Applications of Bio-Inspired Artificial Neural Networks . Springer, 1999, pp. 117–128

1999

Earlier work this paper cites.

——, “Implementability restrictions of the beta-cmos artificial neuron,” in Electronics, Circuits and Systems, 1999. Proceedings of ICECS’99. The 6th IEEE International Conference on , vol. 1. IEEE, 1999, pp. 401–405

1999

Earlier work this paper cites.

C. Rasche and R. J. Douglas, “Silicon synaptic conductances,” Journal of computational neuroscience , vol. 7, no. 1, pp. 33–39, 1999

1999

Earlier work this paper cites.

S. Fusi and M. Mattia, “Collective behavior of networks with linear (vlsi) integrate-and-fire neurons,” Neural Computation , vol. 11, no. 3, pp. 633–652, 1999

1999

Earlier work this paper cites.

M. Glover, A. Hamilton, and L. S. Smith, “Using analogue vlsi leaky integrate-and-fire neurons in a sound analysis system,” in Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, 1999. MicroNeuro’99. Proceedings of the Seventh International Conference on . IEEE, 1999, pp. 90–95

1999

Earlier work this paper cites.

P. Häfliger and M. Mahowald, “Spike based normalizing hebbian learning in an analog vlsi artificial neuron,” Analog Integrated Circuits and Signal Processing , vol. 18, no. 2-3, pp. 133–139, 1999

1999

Earlier work this paper cites.

I. Bayraktaroğlu, A. S. Öğrenci, G. Dündar, S. Balkır, and E. Alpaydın, “Annsys: an analog neural network synthesis system,” Neural networks , vol. 12, no. 2, pp. 325–338, 1999

1999

Earlier work this paper cites.

G. Bo, D. Caviglia, H. Chiblé, and M. Valle, “A circuit architecture for analog on-chip back propagation learning with local learning rate adaptation,” Analog Integrated Circuits and Signal Processing , vol. 18, no. 2-3, pp. 163–173, 1999

1999

Earlier work this paper cites.

——, “Active noise canceling using analog neuro-chip with on-chip learning capability,” in Advances in Neural Information Processing Systems , 1999, pp. 664–670

1999

Earlier work this paper cites.

B. Foruzandeh and S. F. Quigley, “An analogue multilayer perceptron circuit with on-chip training,” in Circuits and Systems, 1999. ISCAS’99. Proceedings of the 1999 IEEE International Symposium on , vol. 5. IEEE, 1999, pp. 395–398

1999

Earlier work this paper cites.

B. Foruzandeh and S. Quigley, “An investigation of the effect of synapse transfer characteristic on the performance of analogue neural networks,” in Electronics, Circuits and Systems, 1999. Proceedings of ICECS’99. The 6th IEEE International Conference on , vol. 2. IEEE, 1999, pp. 1017–1020

1999

Earlier work this paper cites.

J. Liu and M. Brooke, “A fully parallel learning neural network chip for real-time control,” in Neural Networks, 1999. IJCNN’99. International Joint Conference on , vol. 4. IEEE, 1999, pp. 2323–2328

1999

Earlier work this paper cites.

——, “Fully parallel on-chip learning hardware neural network for real-time control,” in Circuits and Systems, 1999. ISCAS’99. Proceedings of the 1999 IEEE International Symposium on , vol. 5. IEEE, 1999, pp. 371–374

1999

Earlier work this paper cites.

M. Masmoudi, M. Samet, F. Taktak, and A. M. Alimi, “A hardware implementation of neural network for the recognition of printed numerals,” in Microelectronics, 1999. ICM’99. The Eleventh International Conference on . IEEE, 1999, pp. 113–116

1999

Earlier work this paper cites.

I. P. Morns and S. S. Dlay, “Analog design of a new neural network for optical character recognition,” IEEE transactions on neural networks , vol. 10, no. 4, pp. 951–953, 1999

1999

Earlier work this paper cites.

A. Bermak and D. Martinez, “Digital vlsi implementation of a multi-precision neural network classifier,” in Neural Information Processing, 1999. Proceedings. ICONIP’99. 6th International Conference on , vol. 2. IEEE, 1999, pp. 560–565

1999

Earlier work this paper cites.

Y. Maeda, A. Nakazawa, and Y. Kanata, “Hardware implementation of a pulse density neural network using simultaneous perturbation learning rule,” Analog Integrated Circuits and Signal Processing , vol. 18, no. 2-3, pp. 153–162, 1999

1999

Earlier work this paper cites.

A. Schmid, Y. Leblebici, and D. Mlynek, “A two-stage charge-based analog/digital neuron circuit with adjustable weights,” in Neural Networks, 1999. IJCNN’99. International Joint Conference on , vol. 4. IEEE, 1999, pp. 2357–2362

1999

Earlier work this paper cites.

J. Yang, M. Ahmadi, G. A. Jullien, and W. C. Miller, “An in-the-loop training method for vlsi neural networks,” in Circuits and Systems, 1999. ISCAS’99. Proceedings of the 1999 IEEE International Symposium on , vol. 5. IEEE, 1999, pp. 619–622

1999

Earlier work this paper cites.

N. Izeboudjen, A. Farah, S. Titri, and H. Boumeridja, “Digital implementation of artificial neural networks: from vhdl description to fpga implementation,” in Engineering Applications of Bio-Inspired Artificial Neural Networks . Springer, 1999, pp. 139–148

1999

Earlier work this paper cites.

H. Hikawa, “Frequency-based multilayer neural network with on-chip learning and enhanced neuron characteristics,” Neural Networks, IEEE Transactions on , vol. 10, no. 3, pp. 545–553, 1999

1999

Earlier work this paper cites.

——, “Using on-line arithmetic and reconfiguration for neuroprocessor implementation,” in International Work-Conference on Artificial Neural Networks . Springer, 1999, pp. 129–138

1999

Earlier work this paper cites.

M. A. A. León, A. R. Castro, and R. R. L. Ascencio, “An artificial neural network on a field programmable gate array as a virtual sensor,” in Design of Mixed-Mode Integrated Circuits and Applications, 1999. Third International Workshop on . IEEE, 1999, pp. 114–117

1999

Earlier work this paper cites.

J. Zhu, G. J. Milne, and B. Gunther, “Towards an fpga based reconfigurable computing environment for neural network implementations,” 1999

1999

Earlier work this paper cites.

G. Minchin and A. Zaknich, “A design for fpga implementation of the probabilistic neural network,” in Neural Information Processing, 1999. Proceedings. ICONIP’99. 6th International Conference on , vol. 2. IEEE, 1999, pp. 556–559

1999

Earlier work this paper cites.

M. Salerno, F. Sargeni, and V. Bonaiuto, “A dedicated multi-chip programmable system for cellular neural networks,” Analog Integrated Circuits and Signal Processing , vol. 18, no. 2-3, pp. 277–288, 1999

1999

Earlier work this paper cites.

Y. Ota and B. M. Wilamowski, “Analog implementation of pulse-coupled neural networks,” Neural Networks, IEEE Transactions on , vol. 10, no. 3, pp. 539–544, 1999

1999

Earlier work this paper cites.

A. Schmid, Y. Leblebici, and D. Mlynek, “Mixed analogue–digital artificial-neural-network architecture with on-chip learning,” IEE Proceedings-Circuits, Devices and Systems , vol. 146, no. 6, pp. 345–349, 1999

1999

Earlier work this paper cites.

M. Schafer and G. Hartmann, “A flexible hardware architecture for online hebbian learning in the sender-oriented pcnn-neurocomputer spike 128 k,” in Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, 1999. MicroNeuro’99. Proceedings of the Seventh International Conference on . IEEE, 1999, pp. 316–323

1999

Earlier work this paper cites.

E. J. Brauer, J. J. Abbas, B. Callaway, J. Colvin, and J. Farris, “Hardware implementation of a neural network pattern shaper algorithm,” in Neural Networks, 1999. IJCNN’99. International Joint Conference on , vol. 4. IEEE, 1999, pp. 2315–2318

1999

Earlier work this paper cites.

J. M. Moreno, J. Cabestany, E. Cantó, J. Faura, and J. M. Insenser, “The role of dynamic reconfiguration for implementing artificial neural networks models in programmable hardware,” in Engineering Applications of Bio-Inspired Artificial Neural Networks . Springer, 1999, pp. 85–94

1999

Earlier work this paper cites.

J. Georgiou, E. M. Drakakis, C. Toumazou, and P. Premanoj, “An analogue micropower log-domain silicon circuit for the hodgkin and huxley nerve axon,” in Circuits and Systems, 1999. ISCAS’99. Proceedings of the 1999 IEEE International Symposium on , vol. 2. IEEE, 1999, pp. 286–289

1999

Earlier work this paper cites.

G. Indiveri, “Neuromorphic analog vlsi sensor for visual tracking: Circuits and application examples,” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on , vol. 46, no. 11, pp. 1337–1347, 1999

1999

Earlier work this paper cites.

T. Morie, K. Uchimura, and Y. Amemiya, “Analog lsi implementation of self-learning neural networks,” Computers & Electrical Engineering , vol. 25, no. 5, pp. 339–355, 1999

1999

Earlier work this paper cites.

V. Douence, A. Laflaquière, S. Le Masson, T. Bal, and G. Le Masson, “Analog electronic system for simulating biological neurons,” in Engineering Applications of Bio-Inspired Artificial Neural Networks . Springer, 1999, pp. 188–197

1999

Earlier work this paper cites.

M. Al-Nsour and H. S. Abdel-Aty-Zohdy, “Analog computational circuits for neural network implementations,” in Electronics, Circuits and Systems, 1999. Proceedings of ICECS’99. The 6th IEEE International Conference on , vol. 1. IEEE, 1999, pp. 299–302

1999

Earlier work this paper cites.

S. D. Roy, A. Chaudhary et al. , “Compact analogue neural network: a new paradigm for neural based combinatorial optimisation,” in Circuits, Devices and Systems, IEE Proceedings- , vol. 146, no. 3. IET, 1999, pp. 111–116

1999

Earlier work this paper cites.

A. B. Torralba and J. Herault, “An efficient neuromorphic analog network for motion estimation,” Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on , vol. 46, no. 2, pp. 269–280, 1999

1999

Earlier work this paper cites.

J. Cosp, J. Madrenas, and J. Cabestany, “A vlsi implementation of a neuromorphic network for scene segmentation,” in Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, 1999. MicroNeuro’99. Proceedings of the Seventh International Conference on . IEEE, 1999, pp. 403–408

1999

Earlier work this paper cites.

T. K. Horiuchi and C. Koch, “Analog vlsi-based modeling of the primate oculomotor system,” Neural Computation , vol. 11, no. 1, pp. 243–265, 1999

1999

Earlier work this paper cites.

G. Indiveri, A. M. Whatley, and J. Kramer, “A reconfigurable neuromorphic vlsi multi-chip system applied to visual motion computation,” in Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, 1999. MicroNeuro’99. Proceedings of the Seventh International Conference on . IEEE, 1999, pp. 37–44

1999

Earlier work this paper cites.

C. M. Higgins and C. Koch, “Multi-chip neuromorphic motion processing,” in Advanced Research in VLSI, 1999. Proceedings. 20th Anniversary Conference on . IEEE, 1999, pp. 309–323

1999

Earlier work this paper cites.

P. Hafliger and C. Rasche, “Floating gate analog memory for parameter and variable storage in a learning silicon neuron,” in Circuits and Systems, 1999. ISCAS’99. Proceedings of the 1999 IEEE International Symposium on , vol. 2. IEEE, 1999, pp. 416–419

1999

Earlier work this paper cites.

K. D. Maier, C. Beckstein, R. Blickhan, W. Erhard, and D. Fey, “A multi-layer-perceptron neural network hardware based on 3d massively parallel optoelectronic circuits,” in Parallel Interconnects, 1999.(PI’99) Proceedings. The 6th International Conference on . IEEE, 1999, pp. 73–80

1999

Earlier work this paper cites.

S.-M. Yoon, E. Tokumitsu, and H. Ishiwara, “An electrically modifiable synapse array composed of metal-ferroelectric-semiconductor (mfs) fet’s using srbi/sub 2/ta/sub 2/o/sub 9/thin films,” Electron Device Letters, IEEE , vol. 20, no. 5, pp. 229–231, 1999

1999

Earlier work this paper cites.

——, “Adaptive-learning neuron integrated circuits using metal-ferroelectric (srbi/sub 2/ta/sub 2/o/sub 9/)-semiconductor (mfs) fet’s,” Electron Device Letters, IEEE , vol. 20, no. 10, pp. 526–528, 1999

1999

Earlier work this paper cites.

——, “Realization of adaptive learning function in a neuron circuit using metal/ferroelectric (srbi2ta2o9)/semiconductor field effect transistor (mfsfet),” Japanese journal of applied physics , vol. 38, no. 4S, p. 2289, 1999

1999

Earlier work this paper cites.

K. Boahen, “A throughput-on-demand address-event transmitter for neuromorphic chips,” in Advanced Research in VLSI, 1999. Proceedings. 20th Anniversary Conference on . IEEE, 1999, pp. 72–86

1999

Earlier work this paper cites.

S. R. Deiss, R. J. Douglas, A. M. Whatley et al. , “A pulse-coded communications infrastructure for neuromorphic systems,” Pulsed neural networks , pp. 157–178, 1999

1999

Earlier work this paper cites.

E. Kim and D. Y. Cho, “Multilayer perceptron with on-chip learning using stochastic ratio pulse arithmetic,” in Neural Information Processing, 1999. Proceedings. ICONIP’99. 6th International Conference on , vol. 2. IEEE, 1999, pp. 566–569

1999

Earlier work this paper cites.

G. N. Patel, G. S. Cymbalyuk, R. L. Calabrese, and S. P. DeWeerth, “Bifurcation analysis of a silicon neuron,” in Advances in Neural Information Processing Systems , 2000, pp. 731–737

2000

Earlier work this paper cites.

C. Rasche and R. Douglas, “An improved silicon neuron,” Analog integrated circuits and signal processing , vol. 23, no. 3, pp. 227–236, 2000

2000

Earlier work this paper cites.

B. M. Wilamowski, J. Binfet, and M. Kaynak, “Vlsi implementation of neural networks,” International journal of neural systems , vol. 10, no. 03, pp. 191–197, 2000

2000

Earlier work this paper cites.

C. Lu and B. Shi, “Circuit design of an adjustable neuron activation function and its derivative,” Electronics Letters , vol. 36, no. 6, pp. 553–555, 2000

2000

Earlier work this paper cites.

——, “Circuit realization of a programmable neuron transfer function and its derivative,” in ijcnn . IEEE, 2000, p. 4047

2000

Earlier work this paper cites.

S. Fusi, M. Annunziato, D. Badoni, A. Salamon, and D. J. Amit, “Spike-driven synaptic plasticity: theory, simulation, vlsi implementation,” Neural Computation , vol. 12, no. 10, pp. 2227–2258, 2000

2000

Earlier work this paper cites.

H. Chible, “Analog circuit for synapse neural networks vlsi implementation,” in Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on , vol. 2. IEEE, 2000, pp. 1004–1007

2000

Earlier work this paper cites.

D. Hajtáš, D. Ďuračková, and G. Benyon-Tinker, “Switched capacitor-based integrate-and-fire neural network,” in The State of the Art in Computational Intelligence . Springer, 2000, pp. 50–55

2000

Earlier work this paper cites.

G. Indiveri, “Modeling selective attention using a neuromorphic analog vlsi device,” Neural computation , vol. 12, no. 12, pp. 2857–2880, 2000

2000

Earlier work this paper cites.

——, “A 2d neuromorphic vlsi architecture for modeling selective attention,” in Neural Networks, 2000. IJCNN 2000, Proceedings of the IEEE-INNS-ENNS International Joint Conference on , vol. 4. IEEE, 2000, pp. 208–213

2000

Earlier work this paper cites.

T. Schoenauer, S. Atasoy, N. Mehrtash, and H. Klar, “Simulation of a digital neuro-chip for spiking neural networks,” in Neural Networks, 2000. IJCNN 2000, Proceedings of the IEEE-INNS-ENNS International Joint Conference on , vol. 4. IEEE, 2000, pp. 490–495

2000

Earlier work this paper cites.

S. Maya, R. Reynoso, C. Torres, and M. Arias-Estrada, “Compact spiking neural network implementation in fpga,” in Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing . Springer, 2000, pp. 270–276

2000

Earlier work this paper cites.

S. Fusi, P. Del Giudice, and D. J. Amit, “Neurophysiology of a vlsi spiking neural network: Lann21,” in Neural Networks, 2000. IJCNN 2000, Proceedings of the IEEE-INNS-ENNS International Joint Conference on , vol. 3. IEEE, 2000, pp. 121–126

2000

Earlier work this paper cites.

H. Abdelbaki, E. Gelenbe, and S. E. El-Khamy, “Analog hardware implementation of the random neural network model,” in Neural Networks, 2000. IJCNN 2000, Proceedings of the IEEE-INNS-ENNS International Joint Conference on , vol. 4. IEEE, 2000, pp. 197–201

2000

Earlier work this paper cites.

F. Diotalevi, M. Valle, G. Bo, E. Biglieri, and D. Caviglia, “An analog on-chip learning circuit architecture of the weight perturbation algorithm,” in Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on , vol. 1. IEEE, 2000, pp. 419–422

2000

Earlier work this paper cites.

S. Popescu, “Hardware implementation of fast neural networks using cpld,” in Neural Network Applications in Electrical Engineering, 2000. NEUREL 2000. Proceedings of the 5th Seminar on . IEEE, 2000, pp. 121–124

2000

Earlier work this paper cites.

T. Szabó, L. Antoni, G. Horváth, and B. Fehér, “A full-parallel digital implementation for pre-trained nns,” in Neural Networks, 2000. IJCNN 2000, Proceedings of the IEEE-INNS-ENNS International Joint Conference on , vol. 2. IEEE, 2000, pp. 49–54

2000

Earlier work this paper cites.

A. N. Al-Zeftawi, K. M. A. El-Fattah, H. N. Shanan, and T. S. Kamel, “Cmos mixed digital analog reconfigurable neural network with gaussian synapses,” in Electrotechnical Conference, 2000. MELECON 2000. 10th Mediterranean , vol. 3. IEEE, 2000, pp. 1198–1201

2000

Earlier work this paper cites.

T. Morie, J. Funakoshi, M. Nagata, and A. Iwata, “An analog-digital merged neural circuit using pulse width modulation technique,” Analog Integrated Circuits and Signal Processing , vol. 25, no. 3, pp. 319–328, 2000

2000

Earlier work this paper cites.

N. Chujo, S. Kuroyanagi, S. Doki, and S. Okuma, “An iterative calculation method of the neuron model for hardware implementation,” in Industrial Electronics Society, 2000. IECON 2000. 26th Annual Confjerence of the IEEE , vol. 1. IEEE, 2000, pp. 664–671

2000

Earlier work this paper cites.

H. F. Restrepo, R. Hoffmann, A. Perez-Uribe, C. Teuscher, and E. Sanchez, “A networked fpga-based hardware implementation of a neural network application,” in Field-Programmable Custom Computing Machines, 2000 IEEE Symposium on . IEEE, 2000, pp. 337–338

2000

Earlier work this paper cites.

R. Gadea, J. Cerdá, F. Ballester, and A. Mocholí, “Artificial neural network implementation on a single fpga of a pipelined on-line backpropagation,” in Proceedings of the 13th international symposium on System synthesis . IEEE Computer Society, 2000, pp. 225–230

2000

Earlier work this paper cites.

E. Gatt, J. Micallef, and E. Chilton, “An analog vlsi time-delay neural network implementation for phoneme recognition,” Cellular Neural Networks and their Applications (CNNA 2000) , p. 315, 2000

2000

Earlier work this paper cites.

R. Woodburn, A. Astaras, R. Dalzell, A. F. Murray, and D. K. McNeill, “Computing with uncertainty in probabilistic neural networks on silicon,” in Proceedings of Symposium on neural computation , 2000

2000

Earlier work this paper cites.

J. C. Gallagher and J. M. Fiore, “Continuous time recurrent neural networks: a paradigm for evolvable analog controller circuits,” in The Proceedings of the National Aerospace and Electronics Conference . Citeseer, 2000, pp. 299–304

2000

Earlier work this paper cites.

B. Girau, “Digital hardware implementation of 2d compatible neural networks,” in Neural Networks, 2000. IJCNN 2000, Proceedings of the IEEE-INNS-ENNS International Joint Conference on , vol. 3. IEEE, 2000, pp. 506–511

2000

Earlier work this paper cites.

M. A. Lewis, “Toward biomorphic control using custom avlsi chips,” in In Proceedings of IEEE International Conference on Robotics and Automation . Citeseer, 2000

2000

Earlier work this paper cites.

S. Jones, R. Meddis, S. C. Lim, and A. R. Temple, “Toward a digital neuromorphic pitch extraction system,” Neural Networks, IEEE Transactions on , vol. 11, no. 4, pp. 978–987, 2000

2000

Earlier work this paper cites.

G. S. Cymbalyuk, G. N. Patel, R. L. Calabrese, S. P. DeWeerth, and A. H. Cohen, “Modeling alternation to synchrony with inhibitory coupling: A neuromorphic vlsi approach,” Neural computation , vol. 12, no. 10, pp. 2259–2278, 2000

2000

Earlier work this paper cites.

S.-C. Liu, “A neuromorphic avlsi model of global motion processing in the fly,” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on , vol. 47, no. 12, pp. 1458–1467, 2000

2000

Earlier work this paper cites.

R. Pinto, P. Varona, A. Volkovskii, A. Szücs, H. D. Abarbanel, and M. I. Rabinovich, “Synchronous behavior of two coupled electronic neurons,” Physical Review E , vol. 62, no. 2, p. 2644, 2000

2000

Earlier work this paper cites.

G. Bo, D. Caviglia, and M. Valle, “A current-mode two-quadrant multiplier for analogue array-based neural systems,” International journal of electronics , vol. 87, no. 4, pp. 407–411, 2000

2000

Earlier work this paper cites.

R. H. Hahnloser, R. Sarpeshkar, M. A. Mahowald, R. J. Douglas, and H. S. Seung, “Digital selection and analogue amplification coexist in a cortex-inspired silicon circuit,” Nature , vol. 405, no. 6789, pp. 947–951, 2000

2000

Earlier work this paper cites.

G. N. Patel, E. A. Brown, and S. P. DeWeerth, “A neuromorphic vlsi system for modeling the neural control of axial locomotion,” in Advances in neural information processing systems , 2000, pp. 724–730

2000

Earlier work this paper cites.

——, “A modular multi-chip neuromorphic architecture for real-time visual motion processing,” Analog Integrated Circuits and Signal Processing , vol. 24, no. 3, pp. 195–211, 2000

2000

Earlier work this paper cites.

——, “Ferroelectric neuron integrated circuits using srbi 2 ta 2 o 9-gate fet’s and cmos schmitt-trigger oscillators,” Electron Devices, IEEE Transactions on , vol. 47, no. 8, pp. 1630–1635, 2000

2000

Earlier work this paper cites.

——, “Improvement of memory retention characteristics in ferroelectric neuron circuits using a pt/srbi 2ta 2o 9/pt/ti/sio 2/si structure-field effect transistor as a synapse device,” Japanese Journal of Applied Physics , vol. 39, no. 4S, p. 2119, 2000

2000

Earlier work this paper cites.

K. A. Boahen, “Point-to-point connectivity between neuromorphic chips using address events,” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on , vol. 47, no. 5, pp. 416–434, 2000

2000

Earlier work this paper cites.

M. F. Simoni, G. S. Cymbalyuk, M. Q. Sorensen, R. L. Calabrese, and S. P. DeWeerth, “Development of hybrid systems: Interfacing a silicon neuron to a leech heart interneuron,” Advances in neural information processing systems , pp. 173–179, 2001

2001

Earlier work this paper cites.

K. Hynna and K. Boahen, “Space-rate coding in an adaptive silicon neuron,” Neural Networks , vol. 14, no. 6, pp. 645–656, 2001

2001

Earlier work this paper cites.

C. Rasche and R. J. Douglas, “Forward-and backpropagation in a silicon dendrite,” Neural Networks, IEEE Transactions on , vol. 12, no. 2, pp. 386–393, 2001

2001

Earlier work this paper cites.

C. Rasche, “An a vlsi basis for dendritic adaptation,” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on , vol. 48, no. 6, pp. 600–605, 2001

2001

Earlier work this paper cites.

S.-C. Liu and B. A. Minch, “Homeostasis in a silicon integrate and fire neuron,” Advances in Neural Information Processing Systems , pp. 727–733, 2001

2001

Earlier work this paper cites.

D. H. Goldberg, G. Cauwenberghs, and A. G. Andreou, “Analog vlsi spiking neural network with address domain probabilistic synapses,” in Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on , vol. 3. IEEE, 2001, pp. 241–244

2001

Earlier work this paper cites.

——, “Probabilistic synaptic weighting in a reconfigurable network of vlsi integrate-and-fire neurons,” Neural Networks , vol. 14, no. 6, pp. 781–793, 2001

2001

Earlier work this paper cites.

——, “A neuromorphic vlsi device for implementing 2d selective attention systems,” Neural Networks, IEEE Transactions on , vol. 12, no. 6, pp. 1455–1463, 2001

2001

Earlier work this paper cites.

A. van Schaik, “Building blocks for electronic spiking neural networks,” Neural networks , vol. 14, no. 6, pp. 617–628, 2001

2001

Earlier work this paper cites.

G. Indiveri, T. Horiuchi, E. Niebur, and R. Douglas, “A competitive network of spiking vlsi neurons,” in World Congress on Neuroinformatics . Vienna, Austria: ARGESIM/ASIM Verlag, 2001, pp. 443–455

2001

Earlier work this paper cites.

P. Hafliger, “Asynchronous event redirecting in bio-inspired communication,” in Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on , vol. 1. IEEE, 2001, pp. 87–90

2001

Earlier work this paper cites.

A. Bofill, D. Thompson, and A. F. Murray, “Circuits for vlsi implementation of temporally asymmetric hebbian learning,” in Advances in Neural Information processing systems , 2001, pp. 1091–1098

2001

Earlier work this paper cites.

M. Al-Nsour and H. S. Abdel-Aty-Zohdy, “Mos fully analog reinforcement neural network chip,” in Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on , vol. 3. IEEE, 2001, pp. 237–240

2001

Earlier work this paper cites.

C. Lu, B. Shi, and L. Chen, “Hardware implementation of an on-chip bp learning neural network with programmable neuron characteristics and learning rate adaptation,” in Neural Networks, 2001. Proceedings. IJCNN’01. International Joint Conference on , vol. 1. IEEE, 2001, pp. 212–215

2001

Earlier work this paper cites.

——, “A programmable on-chip bp learning neural network with enhanced neuron characteristics,” in Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on , vol. 3. IEEE, 2001, pp. 573–576

2001

Earlier work this paper cites.

C. Lu, B.-X. Shi, and L. Chen, “Implementation of an analog self-learning neural network,” in ASIC, 2001. Proceedings. 4th International Conference on . IEEE, 2001, pp. 262–265

2001

Earlier work this paper cites.

K. Wawryn and B. Strzeszewski, “Current mode circuits for programmable wta neural network,” Analog Integrated Circuits and Signal Processing , vol. 27, no. 1, pp. 49–69, 2001

2001

Earlier work this paper cites.

K. Wawryn and A. Mazurek, “Low power, current mode circuits for programmable neural network,” in Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on , vol. 3. IEEE, 2001, pp. 628–631

2001

Earlier work this paper cites.

H. Hikawa, “Digital pulse mode neural network with simple synapse multiplier,” in Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on , vol. 3. IEEE, 2001, pp. 569–572

2001

Earlier work this paper cites.

J. Binfet and B. M. Wilamowski, “Microprocessor implementation of fuzzy systems and neural networks,” in Neural Networks, 2001. Proceedings. IJCNN’01. International Joint Conference on , vol. 1. IEEE, 2001, pp. 234–239

2001

Earlier work this paper cites.

F. Camboni and M. Valle, “A mixed mode perceptron cell for vlsi neural networks,” in Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on , vol. 1. IEEE, 2001, pp. 377–380

2001

Earlier work this paper cites.

V. E. Koosh and R. Goodman, “Vlsi neural network with digital weights and analog multipliers,” in Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on , vol. 3. IEEE, 2001, pp. 233–236

2001

Earlier work this paper cites.

B. Girau, “On-chip learning of fpga-inspired neural nets,” in Neural Networks, 2001. Proceedings. IJCNN’01. International Joint Conference on , vol. 1. IEEE, 2001, pp. 222–227

2001

Earlier work this paper cites.

G. Acosta and M. Tosini, “A firmware digital neural network for climate prediction applications,” in Intelligent Control, 2001.(ISIC’01). Proceedings of the 2001 IEEE International Symposium on . IEEE, 2001, pp. 127–131

2001

Earlier work this paper cites.

D. F. Wolf, R. A. Romero, and E. Marques, “Using embedded processors in hardware models of artificial neural networks,” in V Simposio Brasileiro de automação inteligente, Brasil , 2001

2001

Earlier work this paper cites.

D. F. Wolf, G. Faria, R. A. Romero, E. Marques, M. A. Teixeira, A. A. Ribeiro, L. C. Fernandes, J. M. Scatena, and R. Mezencio, “A pipeline hardware implementation for an artificial neural network,” in Congresso da Sociedade Brasileira de Computacão–SBC, Encontro Nacional de Inteligência Artificial–ENIA , 2001, pp. 1528–1536

2001

Earlier work this paper cites.

J. C. Gallagher, “A neuromorphic paradigm for extrinsically evolved hybrid analog/digital device controllers: initial explorations,” in Evolvable Hardware, 2001. Proceedings. The Third NASA/DoD Workshop on . IEEE, 2001, pp. 48–55

2001

Earlier work this paper cites.

J. Schemmel, K. Meier, and F. Schürmann, “A vlsi implementation of an analog neural network suited for genetic algorithms,” in Evolvable Systems: From Biology to Hardware . Springer, 2001, pp. 50–61

2001

Earlier work this paper cites.

L. Alvado, J. Tomas, R.-L. Masson, V. Douence et al. , “Design of an analogue asic using subthreshold cmos transistors to model biological neurons,” in Custom Integrated Circuits, 2001, IEEE Conference on. IEEE, 2001, pp. 97–100

2001

Earlier work this paper cites.

R. Jung, E. J. Brauer, and J. J. Abbas, “Real-time interaction between a neuromorphic electronic circuit and the spinal cord,” Neural Systems and Rehabilitation Engineering, IEEE Transactions on , vol. 9, no. 3, pp. 319–326, 2001

2001

Earlier work this paper cites.

S.-C. Liu, J. Kramer, G. Indiveri, T. DelbruÈck, T. Burg, and R. Douglas, “Orientation-selective avlsi spiking neurons,” Neural Networks , vol. 14, no. 6, pp. 629–643, 2001

2001

Earlier work this paper cites.

V. Douence, S. Renaud-Le Masson, S. Saïghi, and G. Le Masson, “A field-programmable conductance array ic for biological neurons modeling,” in Bio-Inspired Applications of Connectionism . Springer, 2001, pp. 31–38

2001

Earlier work this paper cites.

P. Hasler and T. S. Lande, “Overview of floating-gate devices, circuits, and systems,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing , vol. 48, no. 1, pp. 1–3, 2001

2001

Earlier work this paper cites.

R. R. Harrison, J. A. Bragg, P. Hasler, B. A. Minch, and S. P. Deweerth, “A cmos programmable analog memory-cell array using floating-gate circuits,” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on , vol. 48, no. 1, pp. 4–11, 2001

2001

Earlier work this paper cites.

P. Hasler and J. Dugger, “Correlation learning rule in floating-gate pfet synapses,” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on , vol. 48, no. 1, pp. 65–73, 2001

2001

Earlier work this paper cites.

E. Culurciello, R. Etienne-Cummings, and K. Boahen, “Arbitrated address-event representation digital image sensor,” Electronics Letters , vol. 37, no. 24, pp. 1443–1445, 2001

2001

Earlier work this paper cites.

V. Dante, P. Del Giudice, and M. Mattia, “Implementation of neuromorphic systems: from discrete components to analog vlsi chips (testing and communication issues),” ANNALI-ISTITUTO SUPERIORE DI SANITA , vol. 37, no. 2, pp. 231–240, 2001

2001

Earlier work this paper cites.

G. Indiveri, R. Murer, and J. Kramer, “Active vision using an analog vlsi model of selective attention,” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on , vol. 48, no. 5, pp. 492–500, 2001

2001

Earlier work this paper cites.

J. C. Principe, V. G. Tavares, J. G. Harris, and W. J. Freeman, “Design and implementation of a biologically realistic olfactory cortex in analog vlsi,” Proceedings of the IEEE , vol. 89, no. 7, pp. 1030–1051, 2001

2001

Earlier work this paper cites.

K. Saeki, R. Iidaka, Y. Sekine, and K. Aihara, “Hardware neuron models with cmos for auditory neural networks,” in Neural Information Processing, 2002. ICONIP’02. Proceedings of the 9th International Conference on , vol. 3. IEEE, 2002, pp. 1325–1329

2002

Earlier work this paper cites.

W. Gerstner and W. M. Kistler, Spiking neuron models: Single neurons, populations, plasticity . Cambridge university press, 2002

2002

Earlier work this paper cites.

J. A. Bragg, E. A. Brown, P. Hasler, and S. P. DeWeerth, “A silicon model of an adapting motoneuron,” in Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on , vol. 4. IEEE, 2002, pp. IV–261

2002

Earlier work this paper cites.

G. Indiveri, “Circuits for bistable spike-timing-dependent plasticity neuromorphic vlsi synapses,” Advances in Neural Information Processing Systems , vol. 15, 2002

2002

Earlier work this paper cites.

S.-C. Liu and B. A. Minch, “Silicon synaptic adaptation mechanisms for homeostasis and contrast gain control,” Neural Networks, IEEE Transactions on , vol. 13, no. 6, pp. 1497–1503, 2002

2002

Earlier work this paper cites.

——, “Analogue vlsi leaky integrate-and-fire neurons and their use in a sound analysis system,” Analog Integrated Circuits and Signal Processing , vol. 30, no. 2, pp. 91–100, 2002

2002

Earlier work this paper cites.

——, “Neuromorphic bistable vlsi synapses with spike-timing-dependent plasticity,” in NIPS , 2002, pp. 1091–1098

2002

Earlier work this paper cites.

J. Schreiter, U. Ramacher, A. Heittmann, D. Matolin, and R. Schüffny, “Analog implementation for networks of integrate-and-fire neurons with adaptive local connectivity,” in Proceedings of the 2002 12th IEEE Workshop on Neural Networks for Signal Processing . Citeseer, 2002, pp. 657–666

2002

Earlier work this paper cites.

R. J. Vogelstein, F. Tenore, R. Philipp, M. S. Adlerstein, D. H. Goldberg, and G. Cauwenberghs, “Spike timing-dependent plasticity in the address domain,” in Advances in Neural Information Processing Systems , 2002, pp. 1147–1154

2002

Earlier work this paper cites.

——, “Neuropipe-chip: A digital neuro-processor for spiking neural networks,” Neural Networks, IEEE Transactions on , vol. 13, no. 1, pp. 205–213, 2002

2002

Earlier work this paper cites.

C. Gordon and P. Hasler, “Biological learning modeled in an adaptive floating-gate system,” in Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on , vol. 5. IEEE, 2002, pp. V–609

2002

Earlier work this paper cites.

S. G. Hohmann, J. Schemmel, F. Schürmann, and K. Meier, “Exploring the parameter space of a genetic algorithm for training an analog neural network.” in GECCO , 2002, pp. 375–382

2002

Earlier work this paper cites.

——, “An on-chip bp learning neural network with ideal neuron characteristics and learning rate adaptation,” Analog Integrated Circuits and Signal Processing , vol. 31, no. 1, pp. 55–62, 2002

2002

Earlier work this paper cites.

C. Lu, B. Shi, and L. Chen, “Hardware implementation of an expandable on-chip learning neural network with 8-neuron and 64-synapse,” in TENCON’02. Proceedings. 2002 IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering , vol. 3. IEEE, 2002, pp. 1451–1454

2002

Earlier work this paper cites.

——, “A general-purpose neural network with on-chip bp learning,” in Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on , vol. 2. IEEE, 2002, pp. II–520

2002

Earlier work this paper cites.

X. Sun, M. H. Chow, F. H. Leung, D. Xu, Y. Wang, and Y.-S. Lee, “Analogue implementation of a neural network controller for ups inverter applications,” Power Electronics, IEEE Transactions on , vol. 17, no. 3, pp. 305–313, 2002

2002

Earlier work this paper cites.

J. Ayala, M. López-Vallejo et al. , “Design of a pipelined hardware architecture for real-time neural network computations,” in Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on , vol. 1. IEEE, 2002, pp. I–419

2002

Earlier work this paper cites.

A. Bermak and A. Bouzerdoum, “Vlsi implementation of a neural network classifier based on the saturating linear activation function,” in Neural Information Processing, 2002. ICONIP’02. Proceedings of the 9th International Conference on , vol. 2. IEEE, 2002, pp. 981–985

2002

Earlier work this paper cites.

S. B. Yun, Y. J. Kim, S. S. Dong, and C. H. Lee, “Hardware implementation of neural network with expansible and reconfigurable architecture,” in Neural Information Processing, 2002. ICONIP’02. Proceedings of the 9th International Conference on , vol. 2. IEEE, 2002, pp. 970–975

2002

Earlier work this paper cites.

——, “Hardware pulse mode neural network with piecewise linear activation function neurons,” in Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on , vol. 2. IEEE, 2002, pp. II–524

2002

Earlier work this paper cites.

V. F. Koosh and R. M. Goodman, “Analog vlsi neural network with digital perturbative learning,” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on , vol. 49, no. 5, pp. 359–368, 2002

2002

Earlier work this paper cites.

J. Liu, M. A. Brooke, and K. Hirotsu, “A cmos feedforward neural-network chip with on-chip parallel learning for oscillation cancellation,” Neural Networks, IEEE Transactions on , vol. 13, no. 5, pp. 1178–1186, 2002

2002

Earlier work this paper cites.

M. Krips, T. Lammert, and A. Kummert, “Fpga implementation of a neural network for a real-time hand tracking system,” in Electronic Design, Test and Applications, 2002. Proceedings. The First IEEE International Workshop on . IEEE, 2002, pp. 313–317

2002

Earlier work this paper cites.

C.-h. Kung, M. J. Devaney, C.-M. Kung, C.-m. Huang, Y.-j. Wang, and C.-T. Kuo, “The vlsi implementation of an artificial neural network scheme embedded in an automated inspection quality management system,” in Instrumentation and Measurement Technology Conference, 2002. IMTC/2002. Proceedings of the 19th IEEE , vol. 1. IEEE, 2002, pp. 239–244

2002

Earlier work this paper cites.

K. R. Nichols, M. A. Moussa, and S. M. Areibi, “Feasibility of floating-point arithmetic in fpga based artificial neural networks,” in In CAINE . Citeseer, 2002

2002

Earlier work this paper cites.

N. Aibe, M. Yasunaga, I. Yoshihara, and J. H. Kim, “A probabilistic neural network hardware system using a learning-parameter parallel architecture,” in Neural Networks, 2002. IJCNN’02. Proceedings of the 2002 International Joint Conference on , vol. 3. IEEE, 2002, pp. 2270–2275

2002

Earlier work this paper cites.

M. Porrmann, U. Witkowski, H. Kalte, and U. Rückert, “Implementation of artificial neural networks on a reconfigurable hardware accelerator,” in euromicro-pdp . IEEE, 2002, p. 0243

2002

Earlier work this paper cites.

V. De Florio, G. Deconinck, and R. Belmans, “A massively parallel architecture for hopfield-type neural network computers,” in International Conference on Massively Parallel Computing Systems (MPCS?02) , 2002

2002

Earlier work this paper cites.

A. Varma et al. , “A novel digital neural network for the travelling salesman problem,” in Neural Information Processing, 2002. ICONIP’02. Proceedings of the 9th International Conference on , vol. 3. IEEE, 2002, pp. 1320–1324

2002

Earlier work this paper cites.

A. Heittmann and U. Rückert, “Mixed mode vlsi implementation of a neural associative memory,” Analog Integrated Circuits and Signal Processing , vol. 30, no. 2, pp. 159–172, 2002

2002

Earlier work this paper cites.

M. Porrmann, U. Witkowski, H. Kalte, and U. Rückert, “Dynamically reconfigurable hardware?a new perspective for neural network implementations,” in Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream . Springer, 2002, pp. 1048–1057

2002

Earlier work this paper cites.

H. De Garis and M. Korkin, “The cam-brain machine (cbm): an fpga-based hardware tool that evolves a 1000 neuron-net circuit module in seconds and updates a 75 million neuron artificial brain for real-time robot control,” Neurocomputing , vol. 42, no. 1, pp. 35–68, 2002

2002

Earlier work this paper cites.

D. Braendler and T. Hendtlass, “The suitability of particle swarm optimisation for training neural hardware,” in Developments in Applied Artificial Intelligence . Springer, 2002, pp. 190–199

2002

Earlier work this paper cites.

G. Indiveri, “Computation in neuromorphic analog vlsi systems,” in Neural Nets WIRN Vietri-01 . Springer, 2002, pp. 3–20

2002

Earlier work this paper cites.

M. Azhar and K. R. Dimond, “Design of an fpga based adaptive neural controller for intelligent robot navigation,” in Digital System Design, 2002. Proceedings. Euromicro Symposium on . IEEE, 2002, pp. 283–290

2002

Earlier work this paper cites.

D. Braendler, T. Hendtlass, and P. O. Donoghue, “Deterministic bit-stream digital neurons,” Neural Networks, IEEE Transactions on , vol. 13, no. 6, pp. 1514–1525, 2002

2002

Earlier work this paper cites.

A. Heittmann, U. Ramacher, D. Matolin, J. Schreiter, and R. Schüffny, “An analog vlsi pulsed neural network for image segmentation using adaptive connection weights,” in Artificial Neural Networks?ICANN 2002 . Springer, 2002, pp. 1293–1298

2002

Earlier work this paper cites.

K. Rahimi, C. Diorio, C. Hernandez, and M. D. Brockhausen, “A simulation model for floating-gate mos synapse transistors,” in Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on , vol. 2. IEEE, 2002, pp. II–532

2002

Earlier work this paper cites.

M. T. Hagan, H. B. Demuth, and O. D. Jesús, “An introduction to the use of neural networks in control systems,” International Journal of Robust and Nonlinear Control , vol. 12, no. 11, pp. 959–985, 2002

2002

Earlier work this paper cites.

T. Netter and N. Francheschini, “A robotic aircraft that follows terrain using a neuromorphic eye,” in Intelligent Robots and Systems, 2002. IEEE/RSJ International Conference on , vol. 1. IEEE, 2002, pp. 129–134

2002

Earlier work this paper cites.

K. Mathia and J. Clark, “On neural network hardware and programming paradigms,” in Neural Networks, 2002. IJCNN’02. Proceedings of the 2002 International Joint Conference on , vol. 3. IEEE, 2002, pp. 2692–2697

2002

Earlier work this paper cites.

E. M. Izhikevich, “Simple model of spiking neurons,” IEEE Transactions on neural networks , vol. 14, no. 6, pp. 1569–1572, 2003

2003

Earlier work this paper cites.

V. Gorelik, “Silicon approximation to biological neuron,” in Neural Networks, 2003. Proceedings of the International Joint Conference on , vol. 2. IEEE, 2003, pp. 965–970

2003

Earlier work this paper cites.

A. Upegui, C. A. Peña-Reyes, and E. Sanchez, “A functional spiking neuron hardware oriented model,” in Computational Methods in Neural Modeling . Springer, 2003, pp. 136–143

2003

Earlier work this paper cites.

T. Asai, Y. Kanazawa, and Y. Amemiya, “A subthreshold mos neuron circuit based on the volterra system,” Neural Networks, IEEE Transactions on , vol. 14, no. 5, pp. 1308–1312, 2003

2003

Earlier work this paper cites.

G. Indiveri, “A low-power adaptive integrate-and-fire neuron circuit,” in ISCAS (4) , 2003, pp. 820–823

2003

Earlier work this paper cites.

S.-C. Liu, “A wide-field direction-selective avlsi spiking neuron,” in Circuits and Systems, 2003. ISCAS’03. Proceedings of the 2003 International Symposium on , vol. 5. IEEE, 2003, pp. V–829

2003

Earlier work this paper cites.

O. Torres, J. Eriksson, J. M. Moreno, and A. Villa, “Hardware optimization of a novel spiking neuron model for the poetic tissue.” in Artificial Neural Nets Problem Solving Methods . Springer, 2003, pp. 113–120

2003

Earlier work this paper cites.

M. Bañuelos-Saucedo, J. Castillo-Hernández, S. Quintana-Thierry, R. Damián-Zamacona, J. Valeriano-Assem, R. Cervantes, R. Fuentes-González, G. Calva-Olmos, and J. Pérez-Silva, “Implementation of a neuron model using fpgas,” Journal of Applied Research and Technology , vol. 1, no. 03, 2003

2003

Earlier work this paper cites.

H. Hikawa, “A digital hardware pulse-mode neuron with piecewise linear activation function,” Neural Networks, IEEE Transactions on , vol. 14, no. 5, pp. 1028–1037, 2003

2003

Earlier work this paper cites.

R. Z. Shi and T. K. Horiuchi, “A summating, exponentially-decaying cmos synapse for spiking neural systems,” in Advances in neural information processing systems , 2003, p. None

2003

Earlier work this paper cites.

S.-C. Liu, “Analog vlsi circuits for short-term dynamic synapses,” EURASIP Journal on Applied Signal Processing , vol. 2003, pp. 620–628, 2003

2003

Earlier work this paper cites.

M. Boegerhausen, P. Suter, and S.-C. Liu, “Modeling short-term synaptic depression in silicon,” Neural Computation , vol. 15, no. 2, pp. 331–348, 2003

2003

Earlier work this paper cites.

E. Chicca, G. Indiveri, and R. Douglas, “An adaptive silicon synapse,” vol. 1, 2003, pp. I–81–I–84. [Online]. Available: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1205505

2003

Earlier work this paper cites.

B. Linares-Barranco, T. Serrano-Gotarredona, and R. Serrano-Gotarredona, “Compact low-power calibration mini-dacs for neural arrays with programmable weights,” Neural Networks, IEEE Transactions on , vol. 14, no. 5, pp. 1207–1216, 2003

2003

Earlier work this paper cites.

D. Roggen, S. Hofmann, Y. Thoma, and D. Floreano, “Hardware spiking neural network with run-time reconfigurable connectivity in an autonomous robot,” in Evolvable hardware, 2003. proceedings. nasa/dod conference on . IEEE, 2003, pp. 189–198

2003

Earlier work this paper cites.

E. Ros, R. Agis, R. R. Carrillo, and E. M. Ortigosa, “Post-synaptic time-dependent conductances in spiking neurons: Fpga implementation of a flexible cell model,” in Artificial Neural Nets Problem Solving Methods . Springer, 2003, pp. 145–152

2003

Earlier work this paper cites.

J. M. Xicotencatl and M. Arias-Estrada, “Fpga based high density spiking neural network array,” in Field Programmable Logic and Application . Springer, 2003, pp. 1053–1056

2003

Earlier work this paper cites.

E. Chicca, D. Badoni, V. Dante, M. D’Andreagiovanni, G. Salina, L. Carota, S. Fusi, and P. Del Giudice, “A vlsi recurrent network of integrate-and-fire neurons connected by plastic synapses with long-term memory,” Neural Networks, IEEE Transactions on , vol. 14, no. 5, pp. 1297–1307, 2003

2003

Earlier work this paper cites.

A. Bofill-i Petit and A. F. Murray, “Learning temporal correlations in biologically-inspired avlsi,” in Circuits and Systems, 2003. ISCAS’03. Proceedings of the 2003 International Symposium on , vol. 5. IEEE, 2003, pp. V–817

2003

Earlier work this paper cites.

M. El-soud, R. AbdelRassoul, H. H. Soliman, L. M. El-ghanam et al. , “Low-power cmos circuits for analog vlsi programmable neural networks,” in Microelectronics, 2003. ICM 2003. Proceedings of the 15th International Conference on . IEEE, 2003, pp. 14–17

2003

Earlier work this paper cites.

——, “An expandable on-chip bp learning neural network chip,” International journal of electronics , vol. 90, no. 5, pp. 331–340, 2003

2003

Earlier work this paper cites.

M. Milev and M. Hristov, “Analog implementation of ann with inherent quadratic nonlinearity of the synapses,” Neural Networks, IEEE Transactions on , vol. 14, no. 5, pp. 1187–1200, 2003

2003

Earlier work this paper cites.

M. Mirhassani, M. Ahmadi, and W. C. Miller, “A mixed-signal vlsi neural network with on-chip learning,” in Electrical and Computer Engineering, 2003. IEEE CCECE 2003. Canadian Conference on , vol. 1. IEEE, 2003, pp. 591–594

2003

Earlier work this paper cites.

H. Pan, M. Manic, X. Li, and B. Wilamowski, “Multilevel logic multiplier using vlsi neural network,” in Industrial Technology, 2003 IEEE International Conference on , vol. 1. IEEE, 2003, pp. 327–332

2003

Earlier work this paper cites.

B. Noory and V. Groza, “A reconfigurable approach to hardware implementation of neural networks,” in Electrical and Computer Engineering, 2003. IEEE CCECE 2003. Canadian Conference on , vol. 3. IEEE, 2003, pp. 1861–1864

2003

Earlier work this paper cites.

A. Savran and S. Ünsal, “Hardware implementation of a feed forward neural network using fpgas,” in The third International Conference on Electrical and Electronics Engineering (ELECO 2003) , 2003, pp. 3–7

2003

Earlier work this paper cites.

B. Denby, P. Garda, B. Granado, C. Kiesling, J.-C. Prévotet, and A. Wassatsch, “Fast triggering in high-energy physics experiments using hardware neural networks,” Neural Networks, IEEE Transactions on , vol. 14, no. 5, pp. 1010–1027, 2003

2003

Earlier work this paper cites.

E. M. Ortigosa, A. Cañas, E. Ros, and R. R. Carrillo, “Fpga implementation of a perceptron-like neural network for embedded applications,” in Artificial Neural Nets Problem Solving Methods . Springer, 2003, pp. 1–8

2003

Earlier work this paper cites.

E. M. Ortigosa, P. M. Ortigosa, A. Cañas, E. Ros, R. Agís, and J. Ortega, “Fpga implementation of multi-layer perceptrons for speech recognition,” in Field Programmable Logic and Application . Springer, 2003, pp. 1048–1052

2003

Earlier work this paper cites.

W. Qinruo, Y. Bo, X. Yun, and L. Bingru, “The hardware structure design of perceptron with fpga implementation,” in Systems, Man and Cybernetics, 2003. IEEE International Conference on , vol. 1. IEEE, 2003, pp. 762–767

2003

Earlier work this paper cites.

M. M. Syiam, H. Klash, I. Mahmoud, and S. Haggag, “Hardware implementation of neural network on fpga for accidents diagnosis of the multi-purpose research reactor of egypt,” in Microelectronics, 2003. ICM 2003. Proceedings of the 15th International Conference on . IEEE, 2003, pp. 326–329

2003

Earlier work this paper cites.

K. Korekado, T. Morie, O. Nomura, H. Ando, T. Nakano, M. Matsugu, and A. Iwata, “A convolutional neural network vlsi for image recognition using merged/mixed analog-digital architecture,” in Knowledge-Based Intelligent Information and Engineering Systems . Springer, 2003, pp. 169–176

2003

Earlier work this paper cites.

K. K. Likharev, “Neuromorphic cmol circuits,” in Nanotechnology, 2003. IEEE-NANO 2003. 2003 Third IEEE Conference on , vol. 1. IEEE, 2003, pp. 339–342

2003

Earlier work this paper cites.

M. Wakamura and Y. Maeda, “Fpga implementation of hopfield neural network via simultaneous perturbation rule,” in SICE 2003 Annual Conference (IEEE Cat. No. 03TH8734) , 2003

2003

Earlier work this paper cites.

D. Hammerstrom, C. Gao, S. Zhu, and M. Butts, “Fpga implementation of very large associative memories–scaling issues,” 2003

2003

Earlier work this paper cites.

N. Nedjah and L. de Macedo Mourelle, “Stochastic reconfigurable hardware for neural networks,” in Digital System Design, 2003. Proceedings. Euromicro Symposium on . IEEE, 2003, pp. 438–442

2003

Earlier work this paper cites.

——, “Fpga-based hardware architecture for neural networks: binary radix vs. stochastic,” in null . IEEE, 2003, p. 111

2003

Earlier work this paper cites.

H. Chen, P. Fleury, and A. F. Murray, “Minimising contrastive divergence in noisy, mixed-mode vlsi neurons,” in Advances in Neural Information Processing Systems , 2003, p. None

2003

Earlier work this paper cites.

K. Likharev, A. Mayr, I. Muckra, and Ö. Türel, “Crossnets: High-performance neuromorphic architectures for cmol circuits,” Annals of the New York Academy of Sciences , vol. 1006, no. 1, pp. 146–163, 2003

2003

Earlier work this paper cites.

R. Cambio and D. C. Hendry, “Low-power digital neuron for som implementations,” Electronics Letters , vol. 39, no. 5, pp. 448–450, 2003

2003

Earlier work this paper cites.

J.-J. Martínez, F. J. Toledo, and J. Ferrández, “New emulated discrete model of cnn architecture for fpga and dsp applications,” in International Work-Conference on Artificial Neural Networks . Springer, 2003, pp. 33–40

2003

Earlier work this paper cites.

H. Hikawa, “A new digital pulse-mode neuron with adjustable activation function,” Neural Networks, IEEE Transactions on , vol. 14, no. 1, pp. 236–242, 2003

2003

Earlier work this paper cites.

Y. Maeda and T. Tada, “Fpga implementation of a pulse density neural network with learning ability using simultaneous perturbation,” Neural Networks, IEEE Transactions on , vol. 14, no. 3, pp. 688–695, 2003

2003

Earlier work this paper cites.

G. Rachmuth and C.-S. Poon, “Design of a neuromorphic hebbian synapse using analog vlsi,” in Neural Engineering, 2003. Conference Proceedings. First International IEEE EMBS Conference on . IEEE, 2003, pp. 221–224

2003

Earlier work this paper cites.

Y. Kanazawa, T. Asai, and Y. Amemiya, “A hardware depressing synapse and its application to contrast-invariant pattern recognition,” in SICE 2003 Annual Conference , vol. 2. IEEE, 2003, pp. 1558–1563

2003

Earlier work this paper cites.

M. Xiaobin, J. Lianwen, S. Dongsheng, and E. Junxun, “A mixed parallel neural networks computing unit implemented in fpga,” in Neural Networks and Signal Processing, 2003. Proceedings of the 2003 International Conference on , vol. 1. IEEE, 2003, pp. 324–327

2003

Earlier work this paper cites.

D. L. Hung and J. Wang, “Digital hardware realization of a recurrent neural network for solving the assignment problem,” Neurocomputing , vol. 51, pp. 447–461, 2003

2003

Earlier work this paper cites.

M. A. Lewis, R. Etienne-Cummings, M. J. Hartmann, Z. R. Xu, and A. H. Cohen, “An in silico central pattern generator: silicon oscillator, coupling, entrainment, and physical computation,” Biological Cybernetics , vol. 88, no. 2, pp. 137–151, 2003

2003

Earlier work this paper cites.

M. Cheely and T. Horiuchi, “A vlsi model of range-tuned neurons in the bat echolocation system,” in Circuits and Systems, 2003. ISCAS’03. Proceedings of the 2003 International Symposium on , vol. 4. IEEE, 2003, pp. IV–872

2003

Earlier work this paper cites.

J. Cosp and J. Madrenas, “Scene segmentation using neuromorphic oscillatory networks,” Neural Networks, IEEE Transactions on , vol. 14, no. 5, pp. 1278–1296, 2003

2003

Earlier work this paper cites.

P. Merolla and K. A. Boahen, “A recurrent model of orientation maps with simple and complex cells,” Departmental Papers (BE) , p. 26, 2003

2003

Earlier work this paper cites.

H. Pan, M. Manic, X. Li, and B. Wilamowski, “Multilevel logic multiplier using vlsi neural network,” in Industrial Technology, 2003 IEEE International Conference on , vol. 1. IEEE, 2003, pp. 327–332

2003

Earlier work this paper cites.

F. Tenore, R. Etienne-Cummings, and M. A. Lewis, “Entrainment of silicon central pattern generators for legged locomotory control,” in Advances in Neural Information Processing Systems , 2003, p. None

2003

Earlier work this paper cites.

Y. Horio, K. Aihara, and O. Yamamoto, “Neuron-synapse ic chip-set for large-scale chaotic neural networks,” Neural Networks, IEEE Transactions on , vol. 14, no. 5, pp. 1393–1404, 2003

2003

Earlier work this paper cites.

B. E. Shi and E. K. Tsang, “A neuromorphic multi-chip model of a disparity selective complex cell,” in Advances in Neural Information Processing Systems , 2003, p. None

2003

Earlier work this paper cites.

L. Alvado, S. Saïghi, J. Tomas, and S. Renaud, “An exponential-decay synapse integrated circuit for bio-inspired neural networks.” in Computational Methods in Neural Modeling . Springer, 2003, pp. 670–677

2003

Earlier work this paper cites.

S. Aunet and M. Hartmann, “Real-time reconfigurable linear threshold elements and some applications to neural hardware,” in Evolvable Systems: From Biology to Hardware . Springer, 2003, pp. 365–376

2003

Earlier work this paper cites.

T. Morie, T. Matsuura, M. Nagata, and A. Iwata, “A multinanodot floating-gate mosfet circuit for spiking neuron models,” Nanotechnology, IEEE Transactions on , vol. 2, no. 3, pp. 158–164, 2003

2003

Earlier work this paper cites.

A. Bermak, “A highly scalable 3d chip for binary neural network classification applications,” in Circuits and Systems, 2003. ISCAS’03. Proceedings of the 2003 International Symposium on , vol. 5. IEEE, 2003, pp. V–685

2003

Earlier work this paper cites.

E. Culurciello, R. Etienne-Cummings, and K. A. Boahen, “A biomorphic digital image sensor,” Solid-State Circuits, IEEE Journal of , vol. 38, no. 2, pp. 281–294, 2003

2003

Earlier work this paper cites.

G. Indiveri, “Neuromorphic selective attention systems,” in Circuits and Systems, 2003. ISCAS’03. Proceedings of the 2003 International Symposium on , vol. 3. IEEE, 2003, pp. III–770

2003

Earlier work this paper cites.

N. Y.-M. Shen, Z. Liu, C. Lee, B. Minch, E. C.-C. Kan et al. , “Charge-based chemical sensors: a neuromorphic approach with chemoreceptive neuron mos (c ν \nu mos) transistors,” Electron Devices, IEEE Transactions on , vol. 50, no. 10, pp. 2171–2178, 2003

2003

Earlier work this paper cites.

S. Sato, K. Nemoto, S. Akimoto, M. Kinjo, and K. Nakajima, “Implementation of a new neurochip using stochastic logic,” Neural Networks, IEEE Transactions on , vol. 14, no. 5, pp. 1122–1127, 2003

Original

2003

Earlier work this paper cites.

E. M. Izhikevich, “Which model to use for cortical spiking neurons?” IEEE transactions on neural networks , vol. 15, no. 5, pp. 1063–1070, 2004

2004

Earlier work this paper cites.

M. F. Simoni, G. S. Cymbalyuk, M. E. Sorensen, R. L. Calabrese, and S. P. DeWeerth, “A multiconductance silicon neuron with biologically matched dynamics,” Biomedical Engineering, IEEE Transactions on , vol. 51, no. 2, pp. 342–354, 2004

2004

Earlier work this paper cites.

M. Sekerli and R. Butera, “An implementation of a simple neuron model in field programmable analog arrays,” in Engineering in Medicine and Biology Society, 2004. IEMBS’04. 26th Annual International Conference of the IEEE , vol. 2. IEEE, 2004, pp. 4564–4567

2004

Earlier work this paper cites.

Y. J. Lee, J. Lee, Y.-B. Kim, J. Ayers, A. Volkovskii, A. Selverston, H. Abarbanel, and M. Rabinovich, “Low power real time electronic neuron vlsi design using subthreshold technique,” in Circuits and Systems, 2004. ISCAS’04. Proceedings of the 2004 International Symposium on , vol. 4. IEEE, 2004, pp. IV–744

2004

Earlier work this paper cites.

A. Upegui, C. A. Peña-Reyes, and E. Sánchez, “A hardware implementation of a network of functional spiking neurons with hebbian learning,” in Biologically Inspired Approaches to Advanced Information Technology . Springer, 2004, pp. 233–243

2004

Earlier work this paper cites.

D. B.-d. Rubin, E. Chicca, and G. Indiveri, “Characterizing the firing proprieties of an adaptive analog vlsi neuron,” in In MM Auke Jan Ijspeert & N. Wakamiya (Eds.), Biologically Inspired Approaches to Advanced Information Technology First International Workshop, Bioadit 2004 . Citeseer, 2004

2004

Earlier work this paper cites.

T. Szabo, G. Horv et al. , “An efficient hardware implementation of feed-forward neural networks,” Applied Intelligence , vol. 21, no. 2, pp. 143–158, 2004

2004

Earlier work this paper cites.

K. Basterretxea, J. Tarela, and I. Del Campo, “Approximation of sigmoid function and the derivative for hardware implementation of artificial neurons,” IEE Proceedings-Circuits, Devices and Systems , vol. 151, no. 1, pp. 18–24, 2004

2004

Earlier work this paper cites.

C. Gordon, E. Farquhar, and P. Hasler, “A family of floating-gate adapting synapses based upon transistor channel models,” in Circuits and Systems, 2004. ISCAS’04. Proceedings of the 2004 International Symposium on , vol. 1. IEEE, 2004, pp. I–317

2004

Earlier work this paper cites.

Y. Dan and M.-m. Poo, “Spike timing-dependent plasticity of neural circuits,” Neuron , vol. 44, no. 1, pp. 23–30, 2004

2004

Earlier work this paper cites.

C. Bartolozzi and G. Indiveri, “A neuromorphic selective attention architecture with dynamic synapses and integrate-and-fire neurons,” Proceedings of Brain Inspired Cognitive Systems (BICS 2004) , pp. 1–6, 2004

2004

Earlier work this paper cites.

Y. Kanazawa, T. Asai, M. Ikebe, and Y. Amemiya, “A novel cmos circuit for depressing synapse and its application to contrast-invariant pattern classification and synchrony detection,” International Journal of Robotics and Automation , vol. 19, no. 4, pp. 206–212, 2004

2004

Earlier work this paper cites.

H. K. Riis and P. Hafliger, “Spike based learning with weak multi-level static memory,” in Circuits and Systems, 2004. ISCAS’04. Proceedings of the 2004 International Symposium on , vol. 5. IEEE, 2004, pp. V–393

2004

Earlier work this paper cites.

J. Schemmel, K. Meier, and E. Mueller, “A new vlsi model of neural microcircuits including spike time dependent plasticity,” in Neural Networks, 2004. Proceedings. 2004 IEEE International Joint Conference on , vol. 3. IEEE, 2004, pp. 1711–1716

2004

Earlier work this paper cites.

Z. Yang and A. F. Murray, “A biologically plausible neuromorphic system for object recognition and depth analysis.” in ESANN , 2004, pp. 157–162

2004

Earlier work this paper cites.

T. Asai, “A neuromorphic cmos family and its application,” in International Congress Series , vol. 1269. Elsevier, 2004, pp. 173–176

2004

Earlier work this paper cites.

E. Chicca, G. Indiveri, and R. J. Douglas, “An event-based vlsi network of integrate-and-fire neurons,” in Circuits and Systems, 2004. ISCAS’04. Proceedings of the 2004 International Symposium on , vol. 5. IEEE, 2004, pp. V–357

2004

Earlier work this paper cites.

D. Hajtas and D. Durackova, “The library of building blocks for an” integrate & fire” neural network on a chip,” in Neural Networks, 2004. Proceedings. 2004 IEEE International Joint Conference on , vol. 4. IEEE, 2004, pp. 2631–2636

2004

Earlier work this paper cites.

G. Indiveri, E. Chicca, and R. Douglas, “A vlsi reconfigurable network of integrate-and-fire neurons with spike-based learning synapses,” 2004, pp. 405–410. [Online]. Available: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.4.7558

2004

Earlier work this paper cites.

S.-C. Liu and R. Douglas, “Temporal coding in a silicon network of integrate-and-fire neurons,” Neural Networks, IEEE Transactions on , vol. 15, no. 5, pp. 1305–1314, 2004

2004

Earlier work this paper cites.

R. J. Vogelstein, U. Mallik, and G. Cauwenberghs, “Silicon spike-based synaptic array and address-event transceiver,” in Circuits and Systems, 2004. ISCAS’04. Proceedings of the 2004 International Symposium on , vol. 5. IEEE, 2004, pp. V–385

2004

Earlier work this paper cites.

R. J. Vogelstein, U. Mallik, E. Culurciello, G. Cauwenberghs, and R. Etienne-Cummings, “Saliency-driven image acuity modulation on a reconfigurable array of spiking silicon neurons,” in Advances in neural information processing systems , 2004, pp. 1457–1464

2004

Earlier work this paper cites.

S. Bellis, K. M. Razeeb, C. Saha, K. Delaney, C. O’Mathuna, A. Pounds-Cornish, G. de Souza, M. Colley, H. Hagras, G. Clarke et al. , “Fpga implementation of spiking neural networks-an initial step towards building tangible collaborative autonomous agents,” in Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on . IEEE, 2004, pp. 449–452

2004

Earlier work this paper cites.

H. H. Hellmich and H. Klar, “An fpga based simulation acceleration platform for spiking neural networks,” in Circuits and Systems, 2004. MWSCAS’04. The 2004 47th Midwest Symposium on , vol. 2. IEEE, 2004, pp. II–389

2004

Earlier work this paper cites.

——, “See: a concept for an fpga based emulation engine for spiking neurons with adaptive weights,” in 5th WSEAS Int. Conf. Neural Networks Applications (NNA?04) , 2004, pp. 930–935

2004

Earlier work this paper cites.

A. Bofill-i Petit and A. F. Murray, “Synchrony detection and amplification by silicon neurons with stdp synapses,” Neural Networks, IEEE Transactions on , vol. 15, no. 5, pp. 1296–1304, 2004

2004

Earlier work this paper cites.

M. Oster and S.-C. Liu, “A winner-take-all spiking network with spiking inputs,” in Electronics, Circuits and Systems, 2004. ICECS 2004. Proceedings of the 2004 11th IEEE International Conference on . IEEE, 2004, pp. 203–206

2004

Earlier work this paper cites.

J. P. Abrahamsen, P. Hafliger, and T. S. Lande, “A time domain winner-take-all network of integrate-and-fire neurons,” in Circuits and Systems, 2004. ISCAS’04. Proceedings of the 2004 International Symposium on , vol. 5. IEEE, 2004, pp. V–361

2004

Earlier work this paper cites.

J. Amaral, J. Amaral, C. Santini, R. Tanscheit, M. Vellasco, and M. Pacheco, “Towards evolvable analog artificial neural networks controllers,” in Evolvable Hardware, 2004. Proceedings. 2004 NASA/DoD Conference on . IEEE, 2004, pp. 46–52

2004

Earlier work this paper cites.

M. Mestari, “An analog neural network implementation in fixed time of adjustable-order statistic filters and applications,” Neural Networks, IEEE Transactions on , vol. 15, no. 3, pp. 766–785, 2004

2004

Earlier work this paper cites.

J. Michel and Y. Herve, “Vhdl-ams behavioral model of an analog neural networks based on a fully parallel weight perturbation algorithm using incremental on-chip learning,” in Industrial Electronics, 2004 IEEE International Symposium on , vol. 1. IEEE, 2004, pp. 211–216

2004

Earlier work this paper cites.

H. Faiedh, Z. Gafsi, K. Torki, and K. Besbes, “Digital hardware implementation of a neural network used for classification,” in Microelectronics, 2004. ICM 2004 Proceedings. The 16th International Conference on . IEEE, 2004, pp. 551–554

2004

Earlier work this paper cites.

S. M. Fakhraie, H. Farshbaf, and K. C. Smith, “Scalable closed-boundary analog neural networks,” Neural Networks, IEEE Transactions on , vol. 15, no. 2, pp. 492–504, 2004

2004

Earlier work this paper cites.

J. Fieres, A. Grübl, S. Philipp, K. Meier, J. Schemmel, and F. Schürmann, “A platform for parallel operation of vlsi neural networks,” in Proc. of the 2004 Brain Inspired Cognitive Systems Conference (BICS2004) , 2004

2004

Earlier work this paper cites.

M. Mirhassani, M. Ahmadi, and W. Miller, “A new mixed-signal feed-forward neural network with on-chip learning,” in Neural Networks, 2004. Proceedings. 2004 IEEE International Joint Conference on , vol. 3. IEEE, 2004, pp. 1729–1734

2004

Earlier work this paper cites.

J. Schemmel, S. Hohmann, K. Meier, and F. Schürmann, “A mixed-mode analog neural network using current-steering synapses,” Analog Integrated Circuits and Signal Processing , vol. 38, no. 2-3, pp. 233–244, 2004

2004

Earlier work this paper cites.

P. Ferreira, P. Ribeiro, A. Antunes, and F. Dias, “Artificial neural networks processor–a hardware implementation using a fpga,” Field Programmable Logic and Application , pp. 1084–1086, 2004

2004

Earlier work this paper cites.

S. S. Kim and S. Jung, “Hardware implementation of a real time neural network controller with a dsp and an fpga,” in Robotics and Automation, 2004. Proceedings. ICRA’04. 2004 IEEE International Conference on , vol. 5. IEEE, 2004, pp. 4639–4644

2004

Earlier work this paper cites.

Ş. ONIGA and A. BUCHMAN, “A new method for hardware implementation of artificial neural network used in smart sensors,” in The 10th International Symposium for Design and Technology of Electronic Packages Conference Proceedings, Bucureşti . Citeseer, 2004, pp. 23–26

2004

Earlier work this paper cites.

D. Ferrer, R. González, R. Fleitas, J. P. Acle, and R. Canetti, “Neurofpga-implementing artificial neural networks on programmable logic devices,” in Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings , vol. 3. IEEE, 2004, pp. 218–223

2004

Earlier work this paper cites.

E. Pasero and M. Perri, “Hw-sw codesign of a flexible neural controller through a fpga-based neural network programmed in vhdl,” in Neural Networks, 2004. Proceedings. 2004 IEEE International Joint Conference on , vol. 4. IEEE, 2004, pp. 3161–3165

2004

Earlier work this paper cites.

N. Aibe, R. Mizuno, M. Nakamura, M. Yasunaga, and I. Yoshihara, “Performance evaluation system for probabilistic neural network hardware,” Artificial Life and Robotics , vol. 8, no. 2, pp. 208–213, 2004

2004

Earlier work this paper cites.

N. Bu, T. Hamamoto, T. Tsuji, and O. Fukuda, “Fpga implementation of a probabilistic neural network for a bioelectric human interface,” in Circuits and Systems, 2004. MWSCAS’04. The 2004 47th Midwest Symposium on , vol. 3. IEEE, 2004, pp. iii–29

2004

Earlier work this paper cites.

O. Nomura, T. Morie, K. Korekado, M. Matsugu, and A. Iwata, “A convolutional neural network vlsi architecture using thresholding and weight decomposition,” in Knowledge-Based Intelligent Information and Engineering Systems . Springer, 2004, pp. 995–1001

2004

Earlier work this paper cites.

H. Li, Y. Hayakawa, S. Sato, and K. Nakajima, “A new digital architecture of inverse function delayed neuron with the stochastic logic,” in Circuits and Systems, 2004. MWSCAS’04. The 2004 47th Midwest Symposium on , vol. 2. IEEE, 2004, pp. II–393

2004

Earlier work this paper cites.

A. Rajah and M. K. Hani, “Asic design of a kohonen neural network microchip,” in Semiconductor Electronics, 2004. ICSE 2004. IEEE International Conference on . IEEE, 2004, pp. 4–pp

2004

Earlier work this paper cites.

K. Ben Khalifa, B. Girau, F. Alexandre, and M. Bedoui, “Parallel fpga implementation of self-organizing maps,” in Microelectronics, 2004. ICM 2004 Proceedings. The 16th International Conference on . IEEE, 2004, pp. 709–712

2004

Earlier work this paper cites.

D. Matolin, S. Getzlaff et al. , “An analog vlsi pulsed neural network implementation for image segmentation,” in null . IEEE, 2004, pp. 51–55

2004

Earlier work this paper cites.

D. Matolin, J. Schreiter, R. SCHUFFNY, A. Heittmann, and U. Ramacher, “Simulation and implementation of an analog vlsi pulse-coupled neural network for image segmentation,” in MWSCAS: Midwest symposium on circuits and systems , 2004

2004

Earlier work this paper cites.

S. Haykin, “Neural networks: A comprehensive foundation,” 2004

2004

Earlier work this paper cites.

J. V. Arthur and K. Boahen, “Recurrently connected silicon neurons with active dendrites for one-shot learning,” in Neural Networks, 2004. Proceedings. 2004 IEEE International Joint Conference on , vol. 3. IEEE, 2004, pp. 1699–1704

2004

Earlier work this paper cites.

E. Graas, E. Brown, and R. H. Lee, “An fpga-based approach to high-speed simulation of conductance-based neuron models,” Neuroinformatics , vol. 2, no. 4, pp. 417–435, 2004

2004

Earlier work this paper cites.

L. Alvado, J. Tomas, S. Saıghi, S. Renaud, T. Bal, A. Destexhe, and G. Le Masson, “Hardware computation of conductance-based neuron models,” Neurocomputing , vol. 58, pp. 109–115, 2004

2004

Earlier work this paper cites.

S. Renaud-Le Masson, G. Le Masson, L. Alvado, S. Saıghi, and J. Tomas, “A neural simulation system based on biologically realistic electronic neurons,” Information Sciences , vol. 161, no. 1, pp. 57–69, 2004

2004

Earlier work this paper cites.

A. Van Schaik and S. Shamma, “A neuromorphic sound localizer for a smart mems system,” Analog Integrated Circuits and Signal Processing , vol. 39, no. 3, pp. 267–273, 2004

2004

Earlier work this paper cites.

——, “A programmable array of silicon neurons for the control of legged locomotion,” in Circuits and Systems, 2004. ISCAS’04. Proceedings of the 2004 International Symposium on , vol. 5. IEEE, 2004, pp. V–349

2004

Earlier work this paper cites.

C.-T. Chiang and C.-Y. Wu, “Implantable neuromorphic vision chips,” Electronics Letters , vol. 40, no. 6, pp. 361–363, 2004

2004

Earlier work this paper cites.

K. A. Zaghloul and K. Boahen, “Optic nerve signals in a neuromorphic chip i: Outer and inner retina models,” Biomedical Engineering, IEEE Transactions on , vol. 51, no. 4, pp. 657–666, 2004

2004

Earlier work this paper cites.

K. Zaghloul, K. Boahen et al. , “Optic nerve signals in a neuromorphic chip ii: Testing and results,” Biomedical Engineering, IEEE Transactions on , vol. 51, no. 4, pp. 667–675, 2004

2004

Earlier work this paper cites.

N. Y. Shen, Z. Liu, B. C. Jacquot, B. A. Minch, and E. C. Kan, “Integration of chemical sensing and electrowetting actuation on chemoreceptive neuron mos (c ν \nu mos) transistors,” Sensors and actuators B: chemical , vol. 102, no. 1, pp. 35–43, 2004

2004

Earlier work this paper cites.

K.-S. Oh and K. Jung, “Gpu implementation of neural networks,” Pattern Recognition , vol. 37, no. 6, pp. 1311–1314, 2004

2004

Earlier work this paper cites.

S. Kanoh, M. Imai, and N. Hoshimiya, “Analog lsi neuron model inspired by biological excitable membrane,” Systems and Computers in Japan , vol. 36, no. 6, pp. 84–91, 2005

2005

Earlier work this paper cites.

E. Farquhar and P. Hasler, “A bio-physically inspired silicon neuron,” Circuits and Systems I: Regular Papers, IEEE Transactions on , vol. 52, no. 3, pp. 477–488, 2005

2005

Earlier work this paper cites.

G. Crebbin, “Image segmentation using neuromorphic integrate-and-fire cells,” in Information, Communications and Signal Processing, 2005 Fifth International Conference on . IEEE, 2005, pp. 305–309

2005

Earlier work this paper cites.

X. Zhu, J. Shen, B. Chi, and Z. Wang, “Circuit implementation of multi-thresholded neuron (mtn) using bicmos technology,” in Neural Networks, 2005. IJCNN’05. Proceedings. 2005 IEEE International Joint Conference on , vol. 1. IEEE, 2005, pp. 627–632

2005

Earlier work this paper cites.

A. Deshmukh, J. Morghade, A. Khera, and P. Bajaj, “Binary neural networks–a cmos design approach,” in Knowledge-Based Intelligent Information and Engineering Systems . Springer, 2005, pp. 1291–1296

2005

Earlier work this paper cites.

B. Liu, S. Konduri, R. Minnich, and J. Frenzel, “Implementation of pulsed neural networks in cmos vlsi technology,” in Proceedings of the 4th WSEAS International Conference on Signal Processing, Robotics and Automation . World Scientific and Engineering Academy and Society (WSEAS), 2005, p. 20

2005

Earlier work this paper cites.

V. Srinivasan, J. Dugger, and P. Hasler, “An adaptive analog synapse circuit that implements the least-mean-square learning rule,” in Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on . IEEE, 2005, pp. 4441–4444

2005

Earlier work this paper cites.

J. Huo and A. Murray, “The role of membrane threshold and rate in stdp silicon neuron circuit simulation,” in Artificial Neural Networks: Formal Models and Their Applications–ICANN 2005 . Springer, 2005, pp. 1009–1014

2005

Earlier work this paper cites.

M. Oster, A. M. Whatley, S.-C. Liu, and R. J. Douglas, “A hardware/software framework for real-time spiking systems,” in Artificial Neural Networks: Biological Inspirations–ICANN 2005 . Springer, 2005, pp. 161–166

2005

Earlier work this paper cites.

P. Rocke, J. Maher, and F. Morgan, “Platform for intrinsic evolution of analogue neural networks,” in Reconfigurable Computing and FPGAs, 2005. ReConFig 2005. International Conference on . IEEE, 2005, pp. 8–pp

2005

Earlier work this paper cites.

B. Glackin, T. M. McGinnity, L. P. Maguire, Q. Wu, and A. Belatreche, “A novel approach for the implementation of large scale spiking neural networks on fpga hardware,” in Computational Intelligence and Bioinspired Systems . Springer, 2005, pp. 552–563

2005

Earlier work this paper cites.

S. Johnston, G. Prasad, L. Maguire, and M. McGinnity, “Comparative investigation into classical and spiking neuron implementations on fpgas,” in Artificial Neural Networks: Biological Inspirations–ICANN 2005 . Springer, 2005, pp. 269–274

2005

Earlier work this paper cites.

M. Pearson, I. Gilhespy, K. Gurney, C. Melhuish, B. Mitchinson, M. Nibouche, and A. Pipe, “A real-time, fpga based, biologically plausible neural network processor,” in Artificial Neural Networks: Formal Models and Their Applications–ICANN 2005 . Springer, 2005, pp. 1021–1026

2005

Earlier work this paper cites.

M. J. Pearson, C. Melhuish, A. G. Pipe, M. Nibouche, K. Gurney, B. Mitchinson et al. , “Design and fpga implementation of an embedded real-time biologically plausible spiking neural network processor,” in Field programmable logic and applications, 2005. international conference on . IEEE, 2005, pp. 582–585

2005

Earlier work this paper cites.

A. Upegui, C. A. Peña-Reyes, and E. Sanchez, “An fpga platform for on-line topology exploration of spiking neural networks,” Microprocessors and microsystems , vol. 29, no. 5, pp. 211–223, 2005

2005

Earlier work this paper cites.

J. Dungen and J. Brault, “Simulated control of a tracking mobile robot by four avlsi integrate-and-fire neurons paired into maps,” in Neural Networks, 2005. IJCNN ’05. Proceedings. 2005 IEEE International Joint Conference on , vol. 2, July 2005, pp. 695–699 vol. 2

2005

Earlier work this paper cites.

S. Bridges, M. Figueroa, D. Hsu, and C. Diorio, “A reconfigurable vlsi learning array,” in Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European . IEEE, 2005, pp. 117–120

2005

Earlier work this paper cites.

M. Mirhassani, M. Ahmadi, and W. C. Miller, “Design and implementation of novel multi-layer mixed-signal on-chip neural networks,” in Circuits and Systems, 2005. 48th Midwest Symposium on . IEEE, 2005, pp. 413–416

2005

Earlier work this paper cites.

L. Brunelli, E. U. Melcher, A. V. De Brito, and R. Freire, “A novel approach to reduce interconnect complexity in ann hardware implementation,” in Neural Networks, 2005. IJCNN’05. Proceedings. 2005 IEEE International Joint Conference on , vol. 5. IEEE, 2005, pp. 2861–2866

2005

Earlier work this paper cites.

B. Salem, A. Karim, S. B. Othman, and S. B. Saoud, “Design and implementation of a neural command rule on a fpga circuit,” in Electronics, Circuits and Systems, 2005. ICECS 2005. 12th IEEE International Conference on . IEEE, 2005, pp. 1–4

2005

Earlier work this paper cites.

D. Zhang, H. Li, and S. Y. Foo, “A simplified fpga implementation of neural network algorithms integrated with stochastic theory for power electronics applications,” in Industrial Electronics Society, 2005. IECON 2005. 31st Annual Conference of IEEE . IEEE, 2005, pp. 6–pp

2005

Earlier work this paper cites.

P. O. Domingos, F. M. Silva, and H. C. Neto, “An efficient and scalable architecture for neural networks with backpropagation learning,” in Field Programmable Logic and Applications, 2005. International Conference on . IEEE, 2005, pp. 89–94

2005

Earlier work this paper cites.

R. G. Gironés, R. C. Palero, J. C. Boluda, and A. S. Cortés, “Fpga implementation of a pipelined on-line backpropagation,” Journal of VLSI signal processing systems for signal, image and video technology , vol. 40, no. 2, pp. 189–213, 2005

2005

Earlier work this paper cites.

V. Pandya, S. Areibi, and M. Moussa, “A handel-c implementation of the back-propagation algorithm on field programmable gate arrays,” in Reconfigurable Computing and FPGAs, 2005. ReConFig 2005. International Conference on . IEEE, 2005, pp. 8–pp

2005

Earlier work this paper cites.

Z. Ruan, J. Han, and Y. Han, “Bp neural network implementation on real-time reconfigurable fpga system for a soft-sensing process,” in Neural Networks and Brain, 2005. ICNN&B’05. International Conference on , vol. 2. IEEE, 2005, pp. 959–963

2005

Earlier work this paper cites.

M. B. Carvalho, A. M. Amaral, L. E. da Silva Ramos, C. A. P. da Silva Martins, and P. Ekel, “Artificial neural network engine: Parallel and parameterized architecture implemented in fpga,” in Pattern Recognition and Machine Intelligence . Springer, 2005, pp. 294–299

2005

Earlier work this paper cites.

S. Vitabile, V. Conti, F. Gennaro, and F. Sorbello, “Efficient mlp digital implementation on fpga,” in Digital System Design, 2005. Proceedings. 8th Euromicro Conference on . IEEE, 2005, pp. 218–222

2005

Earlier work this paper cites.

O. Nomura, T. Morie, M. Matsugu, and A. Iwata, “A convolutional neural network vlsi architecture using sorting model for reducing multiply-and-accumulation operations,” in Advances in Natural Computation . Springer, 2005, pp. 1006–1014

2005

Earlier work this paper cites.

J. C. Gallagher, S. K. Boddhu, and S. Vigraham, “A reconfigurable continuous time recurrent neural network for evolvable hardware applications,” in Evolutionary Computation, 2005. The 2005 IEEE Congress on , vol. 3. IEEE, 2005, pp. 2461–2468

2005

Earlier work this paper cites.

G. Kothapalli, “An analogue recurrent neural network for trajectory learning and other industrial applications,” in Industrial Informatics, 2005. INDIN’05. 2005 3rd IEEE International Conference on . IEEE, 2005, pp. 462–467

2005

Earlier work this paper cites.

Y. Maeda and M. Wakamura, “Simultaneous perturbation learning rule for recurrent neural networks and its fpga implementation,” Neural Networks, IEEE Transactions on , vol. 16, no. 6, pp. 1664–1672, 2005

2005

Earlier work this paper cites.

H. Boumeridja, M. Atencia, G. Joya, and F. Sandoval, “Fpga implementation of hopfield networks for systems identification,” in International Work-Conference on Artificial Neural Networks . Springer, 2005, pp. 582–589

2005

Earlier work this paper cites.

T. Kaulmann, M. Ferber, U. Witkowski, and U. Rückert, “Analog vlsi implementation of adaptive synapses in pulsed neural networks,” in Computational Intelligence and Bioinspired Systems . Springer, 2005, pp. 455–462

2005

Earlier work this paper cites.

H. Torikai, H. Hamanaka, and T. Saito, “Novel digital spiking neuron and its pulse-coupled network: spike position coding and multiplex communication,” in Neural Networks, 2005. IJCNN’05. Proceedings. 2005 IEEE International Joint Conference on , vol. 5. IEEE, 2005, pp. 3249–3254

2005

Earlier work this paper cites.

B. Glackin, L. Maguire, T. McGinnity, A. Belatreche, and Q. Wu, “Implementation of a biologically realistic spiking neuron model on fpga hardware,” in Proceedings of the 8th Joint Conference on Information Sciences, vols , 2005, pp. 1–3

2005

Earlier work this paper cites.

T. S. Mak, G. Rachmuth, K. P. Lam, and C.-S. Poon, “Field programmable gate array implementation of neuronal ion channel dynamics,” in Neural Engineering, 2005. Conference Proceedings. 2nd International IEEE EMBS Conference on . IEEE, 2005, pp. 144–148

2005

Earlier work this paper cites.

B. Prieto, J. de Lope, and D. Maravall, “Reconfigurable hardware implementation of neural networks for humanoid locomotion,” in Artificial Intelligence and Knowledge Engineering Applications: A Bioinspired Approach . Springer, 2005, pp. 395–404

2005

Earlier work this paper cites.

R. Weinstein and R. Lee, “Design of high performance physiologically-complex motoneuron models in fpgas,” in Neural Engineering, 2005. Conference Proceedings. 2nd International IEEE EMBS Conference on . IEEE, 2005, pp. 526–528

2005

Earlier work this paper cites.

M. Martincigh and A. Abramo, “A new architecture for digital stochastic pulse-mode neurons based on the voting circuit,” Neural Networks, IEEE Transactions on , vol. 16, no. 6, pp. 1685–1693, 2005

2005

Earlier work this paper cites.

S. Saighi, J. Tomas, Y. Bornat, and S. Renaud, “A conductance-based silicon neuron with dynamically tunable model parameters,” in Neural Engineering, 2005. Conference Proceedings. 2nd International IEEE EMBS Conference on . IEEE, 2005, pp. 285–288

2005

Earlier work this paper cites.

S. Saïghi, J. Tomas, Y. Bornat, and S. Renaud, “A neuromimetic integrated circuit for interactive real-time simulation,” in Artificial Intelligence and Knowledge Engineering Applications: A Bioinspired Approach . Springer, 2005, pp. 338–346

2005

Earlier work this paper cites.

K. Nakada, T. Asai, and H. Hayashi, “A silicon resonate-and-fire neuron based on the volterra system,” in Int. symp. on nonlinear theory and its applications . Citeseer, 2005, pp. 82–85

2005

Earlier work this paper cites.

S. Han, “Biologically plausible vlsi neural network implementation with asynchronous neuron and spike-based synapse,” in Neural Networks, 2005. IJCNN’05. Proceedings. 2005 IEEE International Joint Conference on , vol. 5. IEEE, 2005, pp. 3244–3248

2005

Earlier work this paper cites.

E. Ozalevli and C. M. Higgins, “Reconfigurable biologically inspired visual motion systems using modular neuromorphic vlsi chips,” Circuits and Systems I: Regular Papers, IEEE Transactions on , vol. 52, no. 1, pp. 79–92, 2005

2005

Earlier work this paper cites.

F. Tenore, R. J. Vogelstein, R. Etienne-Cummings, G. Cauwenberghs, M. A. Lewis, and P. Hasler, “A spiking silicon central pattern generator with floating gate synapses [robot control applications],” in Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on . IEEE, 2005, pp. 4106–4109

2005

Earlier work this paper cites.

N. Zhang, D. C. Wunsch et al. , “A switched-resistor approach to hardware implementation of neural networks,” in Fuzzy Systems, 2005. FUZZ’05. The 14th IEEE International Conference on . IEEE, 2005, pp. 336–340

2005

Earlier work this paper cites.

T. Y. W. Choi, P. A. Merolla, J. V. Arthur, K. A. Boahen, and B. E. Shi, “Neuromorphic implementation of orientation hypercolumns,” Circuits and Systems I: Regular Papers, IEEE Transactions on , vol. 52, no. 6, pp. 1049–1060, 2005

2005

Earlier work this paper cites.

A. L. Braga, C. H. Llanos, M. Ayala-Rincón, and R. P. Jacobi, “Vanngen: a flexible cad tool for hardware implementation of artificial neural networks,” in Reconfigurable Computing and FPGAs, 2005. ReConFig 2005. International Conference on . IEEE, 2005, pp. 8–pp

2005

Earlier work this paper cites.

V. Bečanović, R. Hosseiny, and G. Indiveri, “Object tracking using multiple neuromorphic vision sensors,” in RoboCup 2004: Robot Soccer World Cup VIII . Springer, 2005, pp. 426–433

2005

Earlier work this paper cites.

K. Boahen, “Neuromorphic microchips,” Scientific American , vol. 292, no. 5, pp. 56–63, 2005

2005

Earlier work this paper cites.

Z. Luo, H. Liu, and X. Wu, “Artificial neural network computation on graphic process unit,” in Neural Networks, 2005. IJCNN’05. Proceedings. 2005 IEEE International Joint Conference on , vol. 1. IEEE, 2005, pp. 622–626

2005

Earlier work this paper cites.

D. R. Muir, G. Indiveri, and R. Douglas, “Form specifies function: Robust spike-based computation in analog vlsi without precise synaptic weights,” in Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on . IEEE, 2005, pp. 5150–5153

2005

Earlier work this paper cites.

T. C. Pearce, C. Fulvi-Mari, J. A. Covington, F. S. Tan, J. W. Gardner, T. J. Koickal, and A. Hamilton, “Silicon-based neuromorphic implementation of the olfactory pathway,” in Neural Engineering, 2005. Conference Proceedings. 2nd International IEEE EMBS Conference on . IEEE, 2005, pp. 307–312

2005

Earlier work this paper cites.

Z. S. Zumsteg, C. Kemere, S. O’Driscoll, G. Santhanam, R. E. Ahmed, K. V. Shenoy, and T. H. Meng, “Power feasibility of implantable digital spike sorting circuits for neural prosthetic systems,” Neural Systems and Rehabilitation Engineering, IEEE Transactions on , vol. 13, no. 3, pp. 272–279, 2005

2005

Earlier work this paper cites.

L. Reichel, D. Liechti, K. Presser, and S.-C. Liu, “Robot guidance with neuromorphic motion sensors,” in Robotics and Automation, 2005. ICRA 2005. Proceedings of the 2005 IEEE International Conference on . IEEE, 2005, pp. 3540–3544

2005

Earlier work this paper cites.

——, “Range estimation on a robot using neuromorphic motion sensors,” Robotics and Autonomous Systems , vol. 51, no. 2, pp. 167–174, 2005

2005

Earlier work this paper cites.

S. S. Modi, P. R. Wilson, and A. D. Brown, “Power scalable implementation of artificial neural networks,” in Electronics, Circuits and Systems, 2005. ICECS 2005. 12th IEEE International Conference on . IEEE, 2005, pp. 1–4

2005

Earlier work this paper cites.

R. Serrano-Gotarredona, M. Oster, P. Lichtsteiner, A. Linares-Barranco, R. Paz-Vicente, F. Gomez-Rodriguez, H. K. Riis, T. Delbrück, S.-C. Liu, S. Zahnd et al. , “Aer building blocks for multi-layer multi-chip neuromorphic vision systems,” in NIPS , 2005

2005

Earlier work this paper cites.

S. Aunet and V. Beiu, “Ultra low power fault tolerant neural inspired cmos logic,” in Neural Networks, 2005. IJCNN’05. Proceedings. 2005 IEEE International Joint Conference on , vol. 5. IEEE, 2005, pp. 2843–2848

2005

Earlier work this paper cites.

K. Madani, “From integrated circuits technology to silicon grey matter: Hardware implementation of artificial neural networks,” in Information Processing and Security Systems . Springer, 2005, pp. 327–351

2005

Earlier work this paper cites.

S. Binczak, S. Jacquir, J.-M. Bilbault, V. B. Kazantsev, and V. I. Nekorkin, “Experimental study of electrical fitzhugh–nagumo neurons with modified excitability,” Neural Networks , vol. 19, no. 5, pp. 684–693, 2006

2006

Earlier work this paper cites.

J. H. Wijekoon and P. Dudek, “Simple analogue vlsi circuit of a cortical neuron,” in Electronics, Circuits and Systems, 2006. ICECS’06. 13th IEEE International Conference on . IEEE, 2006, pp. 1344–1347

2006

Earlier work this paper cites.

J. V. Arthur and K. Boahen, “Silicon neurons that inhibit to synchronize,” in Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on . IEEE, 2006, pp. 4–pp

2006

Earlier work this paper cites.

J. H. Wittig and K. Boahen, “Silicon neurons that phase-lock,” in Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on . IEEE, 2006, pp. 4–pp

2006

Earlier work this paper cites.

K. M. Hynna and K. Boahen, “Neuronal ion-channel dynamics in silicon,” in Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on . IEEE, 2006, pp. 4–pp

2006

Earlier work this paper cites.

K. Saeki, Y. Hayashi, and Y. Sekine, “Extraction of phase information buried in fluctuation of a pulse-type hardware neuron model using stdp,” in Neural Networks, 2006. IJCNN’06. International Joint Conference on . IEEE, 2006, pp. 1505–1510

2006

Earlier work this paper cites.

H. Torikai, H. Hamanaka, and T. Saito, “Reconfigurable digital spiking neuron and its pulse-coupled network: Basic characteristics and potential applications,” Circuits and Systems II: Express Briefs, IEEE Transactions on , vol. 53, no. 8, pp. 734–738, 2006

2006

Earlier work this paper cites.

H. Torikai, Y. Shimizu, and T. Saito, “Various spike-trains from a digital spiking neuron: Analysis of inter-spike intervals and their modulation,” in Neural Networks, 2006. IJCNN’06. International Joint Conference on . IEEE, 2006, pp. 3860–3867

2006

Earlier work this paper cites.

X. Chen, G. Wang, W. Zhou, S. Chang, and S. Sun, “Efficient sigmoid function for neural networks based fpga design,” in Intelligent Computing . Springer, 2006, pp. 672–677

2006

Earlier work this paper cites.

D. Larkin, A. Kinane, V. Muresan, and N. O?Connor, “An efficient hardware architecture for a neural network activation function generator,” in Advances in Neural Networks-ISNN 2006 . Springer, 2006, pp. 1319–1327

2006

Earlier work this paper cites.

C. Gordon, A. Preyer, K. Babalola, R. J. Butera, and P. Hasler, “An artificial synapse for interfacing to biological neurons,” in Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on . IEEE, 2006, pp. 4–pp

2006

Earlier work this paper cites.

E. Lazaridis, E. M. Drakakis, and M. Barahona, “A biomimetic cmos synapse,” in Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on . IEEE, 2006, pp. 4–pp

2006

Earlier work this paper cites.

Y. Chen, S. Hall, L. McDaid, O. Buiu, and P. Kelly, “A silicon synapse based on a charge transfer device for spiking neural network application,” in Advances in Neural Networks-ISNN 2006 . Springer, 2006, pp. 1366–1373

2006

Earlier work this paper cites.

——, “On the design of a low power compact spiking neuron cell based on charge-coupled synapses,” in Neural Networks, 2006. IJCNN’06. International Joint Conference on . IEEE, 2006, pp. 1511–1517

2006

Earlier work this paper cites.

C. Bartolozzi and G. Indiveri, “Silicon synaptic homeostasis,” Brain Inspired Cognitive Systems 2006 , pp. 1–4, 2006

2006

Earlier work this paper cites.

S. Mitra, S. Fusi, and G. Indiveri, “A vlsi spike-driven dynamic synapse which learns only when necessary,” in Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on . IEEE, 2006, pp. 4–pp

2006

Earlier work this paper cites.

G. M. Tovar, T. Hirose, T. Asai, and Y. Amemiya, “Precisely-timed synchronization among spiking neural circuits on analog vlsis,” in Proc. the 2006 RISP International Workshop on Nonlinear Circuits amd Signal Processing . Citeseer, 2006, pp. 62–65

2006

Earlier work this paper cites.

Y. Wang and S.-C. Liu, “Programmable synaptic weights for an avlsi network of spiking neurons,” in Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on . IEEE, 2006, pp. 4–pp

2006

Earlier work this paper cites.

J. Georgiou, A. G. Andreou, and P. O. Pouliquen, “A mixed analog/digital asynchronous processor for cortical computations in 3d soi-cmos,” in Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on . IEEE, 2006, pp. 4–pp

2006

Earlier work this paper cites.

J. Arthur and K. Boahen, “Learning in silicon: timing is everything,” Advances in neural information processing systems , vol. 18, p. 75, 2006

2006

Cited alongside, same era.

E. Chicca, P. Lichtsteiner, T. Delbruck, G. Indiveri, and R. J. Douglas, “Modeling orientation selectivity using a neuromorphic multi-chip system,” in Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on . IEEE, 2006, pp. 4–pp

2006

Cited alongside, same era.

I. S. Han, “Mixed-signal neuron-synapse implementation for large-scale neural network,” Neurocomputing , vol. 69, no. 16, pp. 1860–1867, 2006

2006

Cited alongside, same era.

——, “A pulse-based neural hardware implementation based on the controlled conductance by mosfet circuit,” in Neural Networks, 2006. IJCNN’06. International Joint Conference on . IEEE, 2006, pp. 2793–2799

2006

Cited alongside, same era.

T. Hindo, “Weight updating floating-gate synapse,” Electronics Letters , vol. 50, no. 17, pp. 1190–1191, 2014

2014

Later among the works it cites.

Y. Irizarry-Valle, A. C. Parker, and N. M. Grzywacz, “An adaptable cmos depressing synapse with detection of changes in input spike rate,” in Circuits and Systems (LASCAS), 2014 IEEE 5th Latin American Symposium on . IEEE, 2014, pp. 1–4

2014

Later among the works it cites.

V. Kornijcuk, O. Kavehei, H. Lim, J. Y. Seok, S. K. Kim, I. Kim, W.-S. Lee, B. J. Choi, and D. S. Jeong, “Multiprotocol-induced plasticity in artificial synapses,” Nanoscale , vol. 6, no. 24, pp. 15 151–15 160, 2014

2014

Later among the works it cites.

H. Ramachandran, S. Weber, S. A. Aamir, and E. Chicca, “Neuromorphic circuits for short-term plasticity with recovery control,” in Circuits and Systems (ISCAS), 2014 IEEE International Symposium on . IEEE, 2014, pp. 858–861

2014

Later among the works it cites.