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2011

An FPGA-based Torus Communication Network

Pivanti, Marcello, Schifano, Sebastiano Fabio, Simma, Hubert

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We describe the design and FPGA implementation of a 3D torus network (TNW) to provide nearest-neighbor communications between commodity multi-core processors.

The aim of this project is to build up tightly interconnected and scalable parallel systems for scientific computing.
The design includes the VHDL code to implement on latest FPGA devices a network processor, which can be accessed by the CPU through a PCIe interface and which controls the external PHYs of the physical links.
Moreover, a Linux driver and a library implementing custom communication APIs are provided.

An FPGA-based Torus Communication Network · Around

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M. Lüscher, Lattice QCD on PCs?
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P. A. Boyle et al., Overview of the QCDSP and QCDOC computers
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G. Bilardi, et al., The Potential of On-Chip Multiprocessing for QCD Machines
2005
Earlier work this paper cites.

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G. Goldrian, et al., QPACE: Quantum Chromodynamics Parallel Computing on the Cell Broadband Engine
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H. Baier, et al., QPACE: power-efficient parallel architecture based on IBM PowerXCell 8i
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http://sourceforge.net/projects/ftnw
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F. Mantovani, et al., in preparation
Original
Cited in the paper.

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