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Across a wide range of hardware scenarios, the computational efficiency and physical size of the arithmetic units significantly influence the speed and footprint of the overall hardware system.
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Prefixrl: Optimization of parallel prefix circuits using deep reinforcement learning
Rajarshi Roy, Jonathan Raiman, Neel Kant, Ilyas Elkin, Robert Kirby, Michael Siu, Stuart Oberman, Saad Godil, and Bryan Catanzaro · 2021
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High-speed adder design space exploration via graph neural processes
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A graph placement methodology for fast chip design
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On joint learning for solving placement and routing in chip design
Ruoyu Cheng and Junchi Yan · 2021
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Training language models to follow instructions with human feedback
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