All Artificial, Less Intelligence: GenAI through the Lens of Formal Verification

Understand

Modern hardware designs have grown increasingly efficient and complex.

• However, they are often susceptible to Common Weakness Enumerations (CWEs).
• This paper is focused on the formal verification of CWEs in a dataset of hardware designs written in SystemVerilog from Regenerative Artificial Intelligence (AI) powered by Large Language Models (LLMs).
• We applied formal verification to categorize each hardware design as vulnerable or CWE-free.