BetterV: Controlled Verilog Generation with Discriminative Guidance

Understand

Due to the growing complexity of modern Integrated Circuits (ICs), there is a need for automated circuit design methods.

• Recent years have seen rising research in hardware design language generation to facilitate the design process.
• In this work, we propose a Verilog generation framework, BetterV, which fine-tunes the large language models (LLMs) on processed domain-specific datasets and incorporates generative discriminators for guidance on particular design demands.
• The Verilog modules are collected, filtered and processed from internet to form a clean and abundant dataset.