Constructive plaquette compilation for the parity architecture

Understand

Parity compilation is the challenge of laying out the required constraints for the parity mapping in a local way.

• We present the first constructive compilation algorithm for the parity architecture using plaquettes for arbitrary higher-order optimization problems.
• This enables adiabatic protocols, where the plaquette layout can natively be implemented, as well as fully parallelized digital circuits.
• The algorithm builds a rectangular layout of plaquettes, where in each layer of the rectangle at least one constraint is added.