Benchmarking Large Language Models for Automated Verilog RTL Code Generation

Understand

Automating hardware design could obviate a significant amount of human error from the engineering process and lead to fewer errors.

• Verilog is a popular hardware description language to model and design digital systems, thus generating Verilog code is a critical first step.
• Emerging large language models (LLMs) are able to write high-quality code in other programming languages.
• In this paper, we characterize the ability of LLMs to generate useful Verilog.