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In this work, we present a learning-based approach to chip placement, one of the most complex and time-consuming stages of the chip design process.
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Capo: Congestion-Driven Placement for Standard-cell and RTL Netlists with Incremental Capability , pp. 97–133
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Proximal policy optimization algorithms, 2017
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Bonnplace: Placement of leading-edge chips by advanced combinatorial algorithms
Brenner, U., Struzyna, M., and Vygen, J · 2008
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Ntuplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints
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Link prediction based on graph neural networks, 2018
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Zhiyao Xie Duke Univeristy, Durham, N. U. . Y.-H. H. . G.-Q. F. . H. R. . S.-Y. F. . Y. C. . J. H · 2018
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Cheng, C., Kahng, A. B., Kang, I., and Wang, L · 2019
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Gdp: Generalized device placement for dataflow graphs, 2019
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