Fabrication process and failure analysis for robust quantum dots in silicon

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We present an improved fabrication process for overlapping aluminum gate quantum dot devices on Si/SiGe heterostructures that incorporates low-temperature inter-gate oxidation, thermal annealing of gate oxide, on-chip electrostatic discharge (ESD) protection, and an optimized interconnect process for thermal budget considerations.

• This process reduces gate-to-gate leakage, damage from ESD, dewetting of aluminum, and formation of undesired alloys in device interconnects.
• Additionally, cross-sectional scanning transmission electron microscopy (STEM) images elucidate gate electrode morphology in the active region as device geometry is varied.
• We show that overlapping aluminum gate layers homogeneously conform to the topology beneath them, independent of gate geometry, and identify critical dimensions in the gate geometry where pattern transfer becomes non-ideal, causing device failure.