Predictable Accelerator Design with Time-Sensitive Affine Types

Understand

Field-programmable gate arrays (FPGAs) provide an opportunity to co-design applications with hardware accelerators, yet they remain difficult to program.

• High-level synthesis (HLS) tools promise to raise the level of abstraction by compiling C or C++ to accelerator designs.
• Repurposing legacy software languages, however, requires complex heuristics to map imperative code onto hardware structures.
• We find that the black-box heuristics in HLS can be unpredictable: changing parameters in the program that should improve performance can counterintuitively yield slower and larger designs.