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The research interest in specialized hardware accelerators for deep neural networks (DNN) spikes recently owing to their superior performance and efficiency.
Why Systolic Architectures?
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GPUWattch: Enabling Energy Optimizations in GPGPUs
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DianNao family: energy-efficient hardware accelerators for machine learning
Y. Chen et al · 2016
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Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks
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Learning to Track at 100 FPS with Deep Regression Networks
D. Held et al · 2016
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Pushing the limits of accelerator efficiency while retaining programmability
T. Nowatzki et al · 2016
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Mask R-CNN
K. He et al · 2017
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DeepLab: Semantic Image Segmentation with Deep Convolutional Nets, Atrous Convolution, and Fully Connected CRFs
L.-C. Chen et al · 2018
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The architectural implications of autonomous driving: Constraints and acceleration
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Euphrates: algorithm-SoC co-design for low-power mobile continuous vision
Y. Zhu et al · 2018
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Programming Tensor Cores in CUDA 9, 2019
J. Appleyard and othersx · 2019
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CUDA Toolkit Documentation v10.1
NVIDIA · 2019
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CUTLASS 1.3
NVIDIA · 2019
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In-Datacenter Performance Analysis of a Tensor Processing Unit
N. P. Jouppi et al · 2017
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NVIDIA Volta GPU Architecture Whitepaper
NVIDIA · 2017
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M. A. Raihan, N. Goli, and T. M. Aamodt · 2019
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