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The success of deep learning has brought forth a wave of interest in computer hardware design to better meet the high demands of neural network inference.
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On-chip memory technology design space explorations for mobile deep neural network accelerators
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Analog/mixed-signal hardware error modeling for deep learning inference
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A 16nm 25mm2 soc with a 54.5x flexibility-efficiency range from dual-core arm cortex-a53 to efpga and cache-coherent accelerators
P. N. Whatmough, S. K. Lee, M. Donato, H. Hsueh, S. Xi, U. Gupta, L. Pentecost, G. G. Ko, D. Brooks, and G. Wei · 2019
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