Fetching the paper…
Reading the bibliography…
Developing deep learning models for resource-constrained Internet-of-Things (IoT) devices is challenging, as it is difficult to achieve both good quality of results (QoR), such as DNN model inference accuracy, and quality of service (QoS), such as inference latency, throughput, and power consumption.
Very deep convolutional networks for large-scale image recognition
Simonyan, K. et al · 2014
Earlier work this paper cites.
Deep residual learning for image recognition
He, K., Zhang, X., Ren, S., and Sun, J · 2016
Earlier work this paper cites.
A high performance FPGA-based accelerator for large-scale convolutional neural networks
Li, H., Fan, X., Jiao, L., Cao, W., Zhou, X., and Wang, L · 2016
Earlier work this paper cites.
An Opencl deep learning accelerator on Arria 10
Aydonat, U., O’Connell, S., Capalija, D., Ling, A. C., and Chiu, G. R · 2017
Earlier work this paper cites.
Ese: Efficient speech recognition engine with sparse lstm on fpga
Han, S., Kang, J., Mao, H., Hu, Y., Li, X., Li, Y., Xie, D., Luo, H., Yao, S., Wang, Y., et al · 2017
Cited alongside, same era.
In-datacenter performance analysis of a tensor processing unit
Jouppi, N. P., Young, C., Patil, N., Patterson, D., Agrawal, G., Bajwa, R., Bates, S., Bhatia, S., Boden, N., Borchers, A., et al · 2017
Cited alongside, same era.
https://github.com/xyzxinyizhang/2018-DAC-System-Design-Contest , 2018
DAC System Design Contest · 2018
Cited alongside, same era.
Pipe-SGD: A Decentralized Pipelined SGD Framework for Distributed Deep Net Training
Li, Y., Yu, M., Li, S., Avestimehr, S., Kim, N. S., and Schwing, A · 2018
Cited alongside, same era.
Design flow of accelerating hybrid extremely low bit-width neural network in embedded FPGA
Wang, J., Lou, Q., Zhang, X., Zhu, C., Lin, Y., and Chen, D · 2018
Later among the works it cites.
A framework for generating high throughput cnn implementations on FPGAs
Zeng, H., Chen, R., Zhang, C., and Prasanna, V · 2018
Later among the works it cites.
DNNBuilder: an automated tool for building high-performance DNN hardware accelerators for FPGAs
Zhang, X., Wang, J., Zhu, C., Lin, Y., Xiong, J., Hwu, W.-m., and Chen, D · 2018
Later among the works it cites.
alphaXiv searches the wider corpus for related work and actual follow-ups.
alphaXiv is searching for related work…