Quantum circuit optimizations for NISQ architectures

Understand

Currently available quantum computing hardware platforms have limited 2-qubit connectivity among their addressable qubits.

• In order to run a generic quantum algorithm on such a platform, one has to transform the initial logical quantum circuit describing the algorithm into an equivalent one that obeys the connectivity restrictions.
• In this work we construct a circuit synthesis scheme that takes as input the qubit connectivity graph and a quantum circuit over the gate set generated by $\{\text{CNOT},R_{Z}\}$ and outputs a circuit that respects the connectivity of the device.
• As a concrete application, we apply our techniques to Google's Bristlecone 72-qubit quantum chip connectivity, IBM's Tokyo 20-qubit quantum chip connectivity, and Rigetti's Acorn 19-qubit quantum chip connectivity.