LazyFP: Leaking FPU Register State using Microarchitectural Side-Channels

Understand

Modern processors utilize an increasingly large register set to facilitate efficient floating point and SIMD computation.

• This large register set is a burden for operating systems, as its content needs to be saved and restored when the operating system context switches between tasks.
• As an optimization, the operating system can defer the context switch of the FPU and SIMD register set until the first instruction is executed that needs access to these registers.
• Meanwhile, the old content is left in place with the hope that the current task might not use these registers at all.