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This book focuses on the use of algorithmic high-level synthesis (HLS) to build application-specific FPGA systems.
Composing multi-ported memories on FPGAs
Charles Eric Laforest, Zimo Li, Tristan O’rourke, Ming G. Liu, and J. Gregory Steffan · 1936
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A method for the construction of minimum-redundancy codes
David A. Huffman · 1952
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An algorithm for the machine calculation of complex fourier series
James W. Cooley and John W. Tukey · 1965
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Fast fourier transforms: for fun and profit
W Morven Gentleman and Gordon Sande · 1966
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Fourier transform computers using CORDIC iterations
Alvin M. Despain · 1974
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Color imaging array, July 1976
Bryce E. Bayer · 1976
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Introduction to VLSI systems , volume 1080
Carver Mead and Lynn Conway · 1980
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Highly concurrent computing structures for matrix arithmetic and signal processing
Hassan M. Ahmed, Jean-Marc Delosme, and Martin Morf · 1982
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Gauss and the history of the fast fourier transform
M. Heideman, D. Johnson, and C. Burrus · 1984
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Pipeline interleaved programmable DSPs: Architecture
Edward A. Lee and David G. Messerschmitt · 1987
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Arithmetic coding for data compression
Ian H. Witten, Radford M. Neal, and John G. Cleary · 1987
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Prefix sums and their applications
Guy E. Blelloch · 1990
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Arithmetic coding encoder and decoder system, February 27 1990
Glen G. Langdon Jr, Joan L. Mitchell, William B. Pennebaker, and Jorma J. Rissanen · 1990
Earlier work this paper cites.
Understanding retiming through maximum average-weight cycles
Marios C. Papaefthymiou · 1991
Earlier work this paper cites.
Numerical recipes in C
Brian P. Flannery, William H. Press, Saul A. Teukolsky, and William Vetterling · 1992
Earlier work this paper cites.
JPEG: Still image data compression standard
William B. Pennebaker · 1992
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The CORDIC algorithm: new results for fast VLSI implementation
Jean Duprat and Jean-Michel Muller · 1993
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Optimizing synchronous circuitry by retiming
C. Leiserson, F. Rose, and J. Saxe · 1993
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Synthesis and optimization of digital circuits
Giovanni De Micheli · 1994
Earlier work this paper cites.
Building a high performance bit-serial processor in an FPGA
Raymond J. Andraka · 1996
Earlier work this paper cites.
FPGA and CPLD architectures: A tutorial
Stephen Brown and Jonathan Rose · 1996
Cited alongside, same era.
DEFLATE compressed data format specification version 1.3
L Peter Deutsch · 1996
Cited alongside, same era.
Behavioral Synthesis: Digital System Design using the Synopsys Behavioral Compiler
David Knapp · 1996
Cited alongside, same era.
VPR: A new packing, placement and routing tool for FPGA research
Vaughn Betz and Jonathan Rose · 1997
Cited alongside, same era.
The art of computer programming: sorting and searching , volume 3
Donald Ervin Knuth · 1998
Cited alongside, same era.
Tradeoff analysis and architecture design of a hybrid hardware/software sorter
Marcus Bednara et al · 2000
Cited alongside, same era.
A streaming high-throughput linear sorter system with contention buffering
Jorge Ortiz et al · 2011
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Optimizing SDRAM bandwidth for custom FPGA loop accelerators
Samuel Bayliss and George A. Constantinides · 2012
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FPGA-accelerated 3D reconstruction using compressive sensing
Jianwen Chen, Jason Cong, Ming Yan, and Yi Zou · 2012
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High-Level Synthesis: Introduction to Chip and System Design
Daniel D. Gajski, Nikil D. Dutt, Allen C.H. Wu, and Steve Y.L. Lin · 2012
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Designing a hardware in the loop wireless digital channel emulator for software defined radio
Janarbek Matai, Pingfan Meng, Lingjuan Wu, Brad T Weals, and Ryan Kastner · 2012
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Sorting networks on FPGAs
Rene Mueller et al · 2012
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Algorithms in C
Robert Sedgewick · 2001
Cited alongside, same era.
SPARK: A Parallelizing Approach to the High-level Synthesis of Digital Circuits
Sumit Gupta, Rajesh Gupta, Nikil Dutt, and Alexandru Nicolau · 2004
Cited alongside, same era.
Huffman decoder used for decoding both advanced audio coding (AAC) and MP3 audio, June 29 2004
Bhaskar Sherigar and Valmiki K. Ramanujan · 2004
Cited alongside, same era.
Floating-point trigonometric functions for FPGAs
J. Detrey and F. de Dinechin · 2007
Cited alongside, same era.
FPGA implementation of high speed fir filters using add and shift method
Shahnam Mirzaei, Anup Hosangadi, and Ryan Kastner · 2007
Cited alongside, same era.
MapReduce: Simplified data processing on large clusters
Jeffrey Dean and Sanjay Ghemawat · 2008
Cited alongside, same era.
Later among the works it cites.
ARM Limited, v1.0 edition, 2013
AMBA AXI and ACE Protocol Specification · 2013
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Guidelines for the Use of the C Language in Critical Systems
MISRA · 2013
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High-level synthesis of dynamic data structures: A case study using Vivado HLS
F. Winterstein, S. Bayliss, and G. A. Constantinides · 2013
Later among the works it cites.
Modular multi-ported SRAM-based memories
Ameer M.S. Abdelhadi and Guy G.F. Lemieux · 2014
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An empirical evaluation of high-level synthesis languages and tools for database acceleration
Oriol Arcas-Abella et al · 2014
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Hardware system synthesis from domain-specific languages
Nivia George, HyoukJoong Lee, David Novo, Tiark Rompf, Kevin J. Brown, Arvind K. Sujeeth, Martin Odersky, Kunle Olukotun, and Paolo Ienne · 2014
Later among the works it cites.
High throughput channel tracking for JTRS wireless channel emulation
Dajung Lee, Janarbek Matai, Brad Weals, and Ryan Kastner · 2014
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Rigel: Flexible multi-rate image processing hardware
James Hegarty, Ross Daly, Zachary DeVito, Jonathan Ragan-Kelley, Mark Horowitz, and Pat Hanrahan · 2016
Later among the works it cites.
Resolve: Generation of high-performance sorting architectures from high-level synthesis
Janarbek Matai, Dustin Richmond, Dajung Lee, Zac Blair, Qiongzhi Wu, Amin Abazari, and Ryan Kastner · 2016
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Accellera, 2.3.2 edition, October 2017
SystemC · 2017
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Dynamic hazard resolution for pipelining irregular loops in high-level synthesis
Steve Dai, Ritchie Zhao, Gai Liu, Shreesha Srinath, Udit Gupta, Christopher Batten, and Zhiru Zhang · 2017
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Plato and the Nerd: The Creative Partnership of Humans and Technology
Edward Ashford Lee · 2017
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Architecture and synthesis for area-efficient pipelining of irregular loop nests
G. Liu, M. Tan, S. Dai, R. Zhao, and Z. Zhang · 2017
Later among the works it cites.