Superconducting Through-Silicon Vias for Quantum Integrated Circuits

R. F. Figueroa, et. al., Control of sidewall slope in silicon vias using SF6/O2 plasma etching in a conventional reactive ion etching tool, Journal of Vacuum Science and Technology B 23, 2226 (2005)

2005

Earlier work this paper cites.

R. Nagarajan, et. al., Development of a novel deep silicon tapered via etch process for through-silicon interconnection in 3-D integrated systems, Electronic Components and Technology Conference, May 30 - June 2, 2006, San Diego, CA, USA, IEEE, 383 (2006)

2006

Earlier work this paper cites.

S. Heraud, et. al., Easy to fill sloped vias for interconnects applications improved control of silicon tapered etch profile,Electronic Components and Technology Conference, 59th (2009)

2009

Earlier work this paper cites.

A Kahouli, Structural and dielectric study of parylene C thin films, Appl. Phys. Lett. 94, 152901 (2009);

2009

Earlier work this paper cites.

A. G. Fowler, M. Mariantoni, J. M. Martinis, and A. N. Cleland, Surface codes: towards practical large-scale quantum computation. Phys. Rev. A 86, 032324 (2012)

2012

Cited alongside, same era.

P. Dixit, et. al., Effect of process gases on fabricating tapered through-silicon vias by continuous SF6/O2/Ar plasma etching, ECS Journal of Solid State Science and Technology, 1 (3) 107 (2012)

2012

Cited alongside, same era.

Lau, J. H., 2013, Through-Silicon Vias for 3D Integration, McGraw-Hill, New York

2013

Cited alongside, same era.

D. Rosenberg, et. al., 3D integrated superconducting qubits. arXiv:1706.04116

Original

Cited in the paper.

URL: https://scscoatings.com/parylene-applications/ electronic-coatings/

Cited in the paper.

J. P. Gambino, S. A. Adderly, J. U. Knickerbocker, An overview of through-silicon-via technology and manufacturing challenges, Microelectronic Engineering; 135, 73 (2015)

2015

Later among the works it cites.

M. Mohseni, et. al., Commercialize quantum technologies in five years, Nature 543, 171, (2017)

2017

Closest in time.

J. Mutus, et. al., H46.00006: 3D integration of superconducting qubits with bump bonds: Part 1, J. Kelly, et. al., H46.00007: 3D integration of superconducting qubits with bump bonds: Part 2, E. Lucero, et. al., H46.00008: 3D integration of superconducting qubits with bump bonds: Part 3, APS March Meeting 2017

2017

Closest in time.