Z. Du, R. Fasthuber, T. Chen, P. Ienne, L. Li, T. Luo, X. Feng, Y. Chen, and O. Temam, “ShiDianNao,” ISCA 2015
2015
Cited alongside, same era.
E. Stromatias, D. Neil, M. Pfeiffer, F. Galluppi, S. B. Furber, and S.-C. Liu, “Robustness of spiking Deep Belief Networks to noise and reduced bit precision of neuro-inspired hardware platforms,” Frontiers in Neuroscience , vol. 9, Jul. 2015
2015
Cited alongside, same era.
M. Schaffner, F. K. Gürkaynak, A. Smolic, and L. Benini, “DRAM or no-DRAM?: Exploring Linear Solver Architectures for Image Domain Warping in 28 nm CMOS,” Proceedings of DATE , pp. 707–712, 2015
2015
Cited alongside, same era.
L. Cavigelli, D. Gschwend, C. Mayer, S. Willi, B. Muheim, and L. Benini, “Origami: A convolutional network accelerator,” in Proceedings of the 25th edition on Great Lakes Symposium on VLSI , 2015
2015
Cited alongside, same era.
M. Rastegari, V. Ordonez, J. Redmon, and A. Farhadi, “XNOR-net: ImageNet classification using binary convolutional neural networks,” in European Conference on Computer Vision . Springer, 2016
2016
Cited alongside, same era.
S. Zhou, Y. Wu, Z. Ni, X. Zhou, H. Wen, and Y. Zou, “DoReFa-net: Training low bitwidth convolutional neural networks with low bitwidth gradients,” arXiv preprint arXiv:1606.06160 , 2016
Original
2016
Cited alongside, same era.
I. Hubara, M. Courbariaux, D. Soudry, R. El-Yaniv, and Y. Bengio, “Quantized neural networks: Training neural networks with low precision weights and activations,” arXiv preprint arXiv:1609.07061 , 2016
Original
2016
Cited alongside, same era.
Y.-H. Chen, T. Krishna, J. Emer, and V. Sze, “Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks,” in IEEE International Solid-State Circuits Conference , 2016
2016
Cited alongside, same era.
B. Moons and M. Verhelst, “A 0.3-2.6 TOPS/W precision-scalable processor for real-time large-scale ConvNets,” IEEE Symposium on VLSI Circuits, Digest of Technical Papers , vol. 2016-Sept, pp. 1–2
2016
Cited alongside, same era.
S. Han, X. Liu, H. Mao, J. Pu, A. Pedram, M. A. Horowitz, and W. J. Dally, “EIE: Efficient Inference Engine on Compressed Deep Neural Network,” arXiv: 1602.01528 , 2016
2016
Cited alongside, same era.
S. Zhang, Z. Du, L. Zhang, H. Lan, S. Liu, L. Li, Q. Guo, T. Chen, and Y. Chen, “Cambricon-X: An accelerator for sparse neural networks,” in Proceedings of the Annual International Symposium on Microarchitecture, MICRO , vol. 2016-Dec. IEEE, oct 2016, pp. 1–12
2016
Cited alongside, same era.
J. Sim, J.-S. Park, M. Kim, D. Bae, Y. Choi, and L.-S. Kim, “14.6 A 1.42 TOPS/W deep convolutional neural network recognition processor for intelligent IoE systems,” in 2016 IEEE International Solid-State Circuits Conference (ISSCC) . IEEE, 2016, pp. 264–265
2016
Cited alongside, same era.