A GPU-Outperforming FPGA Accelerator Architecture for Binary Convolutional Neural Networks

Understand

FPGA-based hardware accelerators for convolutional neural networks (CNNs) have obtained great attentions due to their higher energy efficiency than GPUs.

• However, it is challenging for FPGA-based solutions to achieve a higher throughput than GPU counterparts.
• In this paper, we demonstrate that FPGA acceleration can be a superior solution in terms of both throughput and energy efficiency when a CNN is trained with binary constraints on weights and activations.
• Specifically, we propose an optimized FPGA accelerator architecture tailored for bitwise convolution and normalization that features massive spatial parallelism with deep pipelines stages.