Understand
We describe a programming abstraction for heterogeneous parallel hardware, designed to capture a wide range of popular parallel hardware, including GPUs, vector instruction sets and multicore CPUs.
- Our abstraction, which we call HPVM, is a hierarchical dataflow graph with shared memory and vector instructions.
- We use HPVM to define both a virtual instruction set (ISA) and also a compiler intermediate representation (IR).
- The virtual ISA aims to achieve both functional portability and performance portability across heterogeneous systems, while the compiler IR aims to enable effective code generation and optimization for such systems.
Built on
LLVM: A compilation framework for lifelong program analysis and transformation
Chris Lattner and Vikram Adve · 2004
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