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A fundamental assumption in software security is that a memory location can only be modified by processes that may write to this memory location.
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Park, K., Baeg, S., Wen, S., Wong, R.: Active-Precharge Hammering on a Row Induced Failure in DDR3 SDRAMs under 3x nm Technology. In: IIRW’14 (2014)
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Yarom, Y., Falkner, K.: FLUSH+RELOAD: A High Resolution, Low Noise, L3 Cache Side-Channel Attack. In: USENIX Security’14 (2014)
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Aichinger, B.: DDR memory errors caused by Row Hammer. In: HPEC’15 (2015)
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Aichinger, B.: Row Hammer Failures in DDR Memory. In: memcon’15 (2015)
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Barresi, A., Razavi, K., Payer, M., Gross, T.R.: CAIN: silently breaking ASLR in the cloud. In: WOOT’15 (2015)
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Maurice, C., Neumann, C., Heen, O., Francillon, A.: C5: Cross-Cores Cache Covert Channel. In: DIMVA’15 (2015)
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Oren, Y., Kemerlis, V.P., Sethumadhavan, S., Keromytis, A.D.: The Spy in the Sandbox: Practical Cache Attacks in JavaScript and their Implications. In: CCS’15 (2015)
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Rahmati, A., Hicks, M., Holcomb, D.E., Fu, K.: Probable cause: the deanonymizing effects of approximate DRAM. In: ISCA’15 (2015)
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Seaborn, M.: How physical addresses map to rows and banks in DRAM
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2015
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Gruss, D., Spreitzer, R., Mangard, S.: Cache Template Attacks: Automating Attacks on Inclusive Last-Level Caches. In: USENIX Security’15 (2015)
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Herath, N., Fogh, A.: These are Not Your Grand Daddys CPU Performance Counters - CPU Hardware Performance Counters for Security. Black Hat (2015)
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Inci, M.S., Gulmezoglu, B., Irazoqui, G., Eisenbarth, T., Sunar, B.: Seriously, get off my cloud! Cross-VM RSA Key Recovery in a Public Cloud. Cryptology ePrint Archive, Report 2015/898 pp. 1–15 (2015)
2015
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Irazoqui, G., Eisenbarth, T., Sunar, B.: S$A: A Shared Cache Attack that Works Across Cores and Defies VM Sandboxing – and its Application to AES. In: S&P’15 (2015)
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2015
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Liu, F., Yarom, Y., Ge, Q., Heiser, G., Lee, R.B.: Last-Level Cache Side-Channel Attacks are Practical. In: S&P’15 (2015)
2015
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Seaborn, M., Dullien, T.: Exploiting the DRAM rowhammer bug to gain kernel privileges. In: Black Hat (2015)
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W3C: High Resolution Time Level 2 - W3C Working Draft 21 July 2015
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Wong, H.: Intel Ivy Bridge Cache Replacement Policy
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Yarom, Y., Ge, Q., Liu, F., Lee, R.B., Heiser, G.: Mapping the Intel Last-Level Cache. Cryptology ePrint Archive, Report 2015/905 pp. 1–12 (2015)
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Aweke, Z.B., Yitbarek, S.F., Qiao, R., Das, R., Hicks, M., Oren, Y., Austin, T.: ANVIL: Software-Based Protection Against Next-Generation Rowhammer Attacks. In: ASLPOS’16 (2016)
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Gruss, D., Maurice, C., Wagner, K., Mangard, S.: Flush+Flush: A Fast and Stealthy Cache Attack. In: DIMVA’16 (2016)
2016
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Lanteigne, M.: How Rowhammer Could Be Used to Exploit Weakness Weaknesses in Computer Hardware (March) (2016),
2016
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Payer, M.: HexPADS: a platform to detect “stealth” attacks. In: ESSoS’16 (2016)
2016
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